View AD9516-5PCBZ_8760637.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

14-output clock generator ad9516-5 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2011 analog devices, inc. all rights reserved. features low phase noise, phase-locked loop (pll) external vco/vcxo to 2.4 ghz optional 1 differential or 2 single-ended reference inputs reference monitoring capability automatic revertive and manual reference switchover/holdover modes accepts lvpecl, lvds, or cmos references to 250 mhz programmable delays in path to pfd digital or analog lock detect, selectable six 1.6 ghz lvpecl outputs, arranged in 3 groups each group shares a 1-to-32 divider with coarse phase delay additive output jitter: 225 fs rms channel-to-channel skew paired outputs of <10 ps four 800 mhz lvds outputs, arranged in 2 groups each group has 2 cascaded 1-to-32 dividers with coarse phase delay additive output jitter: 275 fs rms fine delay adjust (t) on each lvds output each lvds output can be reconfigured as two 250 mhz cmos outputs automatic synchronization of all outputs on power-up manual output synchronization available available in 64-lead lfcsp applications low jitter, low phase noise clock distribution 10/40/100 gb/sec networking line cards, including sonet, synchronous ethernet, otu2/3/4 forward error correction (g.710) clocking high speed adcs, dacs, ddss, ddcs, ducs, mxfes high performance wireless transceivers ate and high performance instrumentation general description the ad9516-5 1 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip pll that can be used with an external vco/vcxo of up to 2.4 ghz. the ad9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. functional block diagram refin ref1 ref2 clk refin clk switchover and monitor pll divider and muxes cp status monitor lvpecl lvpecl lvpecl lvds/cmos lvds/cmos serial control port and digital logic ad9516-5 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 div/ div/ div/ div/ div/ div/ div/ ? t ? t ? t ? t 07972-001 figure 1. the ad9516-5 features six lvpecl outputs (in three pairs) and four lvds outputs (in two pairs). each lvds output can be reconfigured as two cmos outputs. the lvpecl outputs operate to 1.6 ghz, the lvds outputs operate to 800 mhz, and the cmos outputs operate to 250 mhz. each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. the range of division for the lvpecl outputs is 1 to 32. the lvds/cmos outputs allow a range of divisions up to a maximum of 1024. the ad9516-5 is available in a 64-lead lfcsp and can be operated from a single 3.3 v supply. an external vco, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (v cp ) to 5.5 v. a separate lvpecl power supply can be from 2.375 v to 3.6 v (nominal). the ad9516-5 is specified for operation over the industrial range of ?40c to +85c. for applications requiring an integrated eeprom, or needing additional outputs, the ad9520-5 and ad9522-5 are available. 1 ad9516 is used throughout the data sheet to refer to all members of the ad9516 family. however, when ad9516-5 is used, it refers to that specific member of the ad9516 family.
ad9516-5 rev. a | page 2 of 76 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications..................................................................................... 4 ? power supply requirements ....................................................... 4 ? pll characteristics ...................................................................... 4 ? clock inputs .................................................................................. 6 ? clock outputs ............................................................................... 6 ? clock output additive phase noise (distribution only; vco divider not used) .............................................................. 7 ? clock output absolute time jitter (clock generation using external vcxo) ................................................................ 8 ? clock output additive time jitter (vco divider not used)....................................................................................... 8 ? clock output additive time jitter (vco divider used) ....... 9 ? delay block additive time jitter................................................ 9 ? serial control port ..................................................................... 10 ? pd , reset , and sync pins ..................................................... 10 ? ld, status, and refmon pins............................................ 11 ? power dissipation....................................................................... 11 ? timing characteristics .............................................................. 13 ? absolute maximum ratings.......................................................... 15 ? thermal resistance .................................................................... 15 ? esd caution................................................................................ 15 ? pin configuration and function descriptions........................... 16 ? typical performance characteristics ........................................... 18 ? terminology .................................................................................... 23 ? detailed block diagram ................................................................ 24 ? theory of operation ...................................................................... 25 ? operational configurations...................................................... 25 ? lock detect ................................................................................. 31 ? clock distribution ..................................................................... 35 ? reset modes ................................................................................ 43 ? power-down modes .................................................................. 43 ? serial control port ......................................................................... 44 ? serial control port pin descriptions....................................... 44 ? general operation of serial control port............................... 44 ? instruction word (16 bits)........................................................ 45 ? msb/lsb first transfers ........................................................... 45 ? thermal performance.................................................................... 48 ? register maps.................................................................................. 49 ? register map overview ............................................................. 49 ? register map descriptions........................................................ 52 ? applications information .............................................................. 71 ? frequency planning using the ad9516 .................................. 71 ? using the ad9516 outputs for adc clock applications .... 71 ? lvpecl clock distribution ..................................................... 72 ? lvds clock distribution .......................................................... 72 ? cmos clock distribution ........................................................ 73 ? outline dimensions ....................................................................... 74 ? ordering guide .......................................................................... 74 ?
ad9516-5 rev. a | page 3 of 76 revision history 8/11rev. 0 to rev. a changes to features, applications, and general description ..... 1 changes to cprset pin resistor parameter, table 1 .................. 4 change to p = 2 dm (2/3) parameter, table 2 .............................. 5 changes test conditions/comments, table 4 .............................. 6 moved table 5 to end of specifications and renumbered sequentially ...................................................................................... 13 change to shortest delay range parameter, test conditions/comments, table 14 .......................................... 13 moved timing diagrams ............................................................... 14 change to endnote, table 16 ......................................................... 15 change to caption, figure 8 .......................................................... 18 change to captions, figure 20 and figure 21 ............................. 20 moved figure 23 and figure 24 ..................................................... 21 added figure 31; renumbered sequentially ............................... 22 change to mode 1clock distribution or external vco < 1600 mhz section .......................................................................... 25 changes to mode 2 (high frequency clock distribution) clk or external vco > 1600 mhz; change to table 22 .......... 26 change to charge pump (cp) section ......................................... 28 changes to pll reference inputs and reference switchover sections ............................................................................................. 29 changes to prescaler section and table 24 .................................. 30 changes to a and b counters, digital lock detect (dld), and current source digital lock detect (csdld) sections .... 31 change to holdover section .......................................................... 32 changes to automatic/internal holdover mode ........................ 34 changes to clock distribution section ........................................ 35 changes to channel dividerslvds/cmos outputs section .............................................................................................. 37 change to the instruction word (16 bits) section ..................... 45 change to figure 53 ........................................................................ 46 changes to ja and jt parameters, table 46 ............................... 48 changes to register address 0x003 and register address 0x01c, table 47 ................................................. 49 changes to register address 0x003, table 48 ............................. 52 changes to register address 0x016, bits[2:0], table 49 ............ 54 changes to register address 0x01c, bits[4:3], table 49 ........... 57 changes to register address 0x191, register address 0x194, and register address 0x197, bit 5, table 53 ................................ 66 added frequency planning using the ad9516 section ............ 71 changes to lvpecl clock distribution and lvds clock distribution sections; changes to figure 59, figure 60, and figure 61 ........................................................................................... 72 1/09revision 0: initial version
ad9516-5 rev. a | page 4 of 76 specifications typical is given for v s = v s_lvpecl = 3.3 v 5%; v s v cp 5.25 v; t a = 25c; r set = 4.12 k; cp rset = 5.1 k, unless otherwise noted. minimum and maximum values are given over full v s and t a (?40c to +85c) variation. power supply requirements table 1. parameter min typ max unit test conditions/comments v s 3.135 3.3 3.465 v 3.3 v 5% v s_lvpecl 2.375 vs v nominally 2.5 v to 3.3 v 5% v cp v s 5.25 v nominally 3.3 v to 5.0 v 5% rset pin resistor 4.12 k sets internal biasing currents; connect to ground cprset pin resistor 2.7 5.1 10 k sets internal cp current range, nominally 4.8 ma (cp_lsb = 600 a); actual current can be calculated by: cp_lsb = 3.06/cprset; connect to ground pll characteristics table 2. parameter min typ max unit test conditions/comments reference inputs differential mode (refin, refin ) differential mode (can accommodate single-ended input by ac grounding undriven input) input frequency 0 250 mhz frequencies below about 1 mhz should be dc-coupled; be careful to match v cm (self-bias voltage) input sensitivity 250 mv p-p pll figure of merit (fom) increases with increasing slew rate; see figure 13 self-bias voltage, refin 1.35 1.60 1.75 v self-bias voltage of refin 1 self-bias voltage, refin 1.30 1.50 1.60 v self-bias voltage of refin 1 input resistance, refin 4.0 4.8 5.9 k self-biased 1 input resistance, refin 4.4 5.3 6.4 k self-biased 1 dual single-ended mode (ref1, ref2) two single-ended cmos-compatible inputs input frequency (ac-coupled) 20 250 mhz slew rate > 50 v/s input frequency (dc-coupled) 0 250 mhz slew rate > 50 v/s; cmos levels input sensitivity (ac-coupled) 0.8 v p-p should not exceed v s p-p input logic high 2.0 v input logic low 0.8 v input current ?100 +100 a input capacitance 2 pf each pin, refin/ refin (ref1/ref2) phase/frequency detector (pfd) pfd input frequency 100 mhz antibacklash pulse width = 1.3 ns, 2.9 ns 45 mhz antibacklash pulse width = 6.0 ns antibacklash pulse width 1.3 ns register 0x017[1:0] = 01b 2.9 ns register 0x017[1:0] = 00b; register 0x017[1:0] = 11b 6.0 ns register 0x017[1:0] = 10b charge pump (cp) i cp sink/source programmable high value 4.8 ma with cp rset = 5.1 k low value 0.60 ma absolute accuracy 2.5 % cp v = v cp /2 cprset range 2.7/10 k i cp high impedance mode leakage 1 na sink-and-source current matching 2 % 0.5 < cp v < v cp ? 0.5 v i cp vs. cp v 1.5 % 0.5 < cp v < v cp ? 0.5 v i cp vs. temperature 2 % v cp = vcp/2 v
ad9516-5 rev. a | page 5 of 76 parameter min typ max unit test conditions/comments prescaler (part of n divider) see the vcxo/vco feedback divider np, a, b section prescaler input frequency p = 1 fd 300 mhz p = 2 fd 600 mhz p = 3 fd 900 mhz p = 2 dm (2/3) 200 mhz p = 4 dm (4/5) 1000 mhz p = 8 dm (8/9) 2400 mhz p = 16 dm (16/17) 3000 mhz p = 32 dm (32/33) 3000 mhz prescaler output frequency 300 mhz a, b counter input frequency (prescaler input frequency divided by p) pll divider delays register 0x019: r, bits[5:3]; n, bits[2:0]; see table 49 000 off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps noise characteristics in-band phase noise of the charge pump/phase frequency detector (in-band is within the lbw of the pll) the pll in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 log(n) (where n is the value of the n divider) at 500 khz pfd frequency ?165 dbc/hz at 1 mhz pfd frequency ?162 dbc/hz at 10 mhz pfd frequency ?151 dbc/hz at 50 mhz pfd frequency ?143 dbc/hz pll figure of merit (fom) ?220 dbc/hz reference slew rate > 0.25 v/ns; fom + 10 log(f pfd ) is an approximation of the pfd/cp in-band phase noise (in the flat region) inside the pll loop bandwidth; when running closed-loop, the phase noise, as observed at the vco output, is increased by 20 log(n) pll digital lock detect window 2 signal available at the ld, status, and refmon pins when selected by appropriate register settings required to lock (coincidence of edges) selected by register 0x017[1:0] and register 0x018[4] low range (abp 1.3 ns, 2.9 ns) 3.5 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 1b high range (abp 1.3 ns, 2.9 ns) 7.5 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 0b high range (abp 6.0 ns) 3.5 ns regist er 0x017[1:0] = 10b; register 0x018[4] = 0b to unlock after lock (hysteresis) 2 low range (abp 1.3 ns, 2.9 ns) 7 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 1b high range (abp 1.3 ns, 2.9 ns) 15 ns register 0x017[1:0] = 00b, 01b, 11b; register 0x018[4] = 0b high range (abp 6.0 ns) 11 ns register 0x017[1:0] = 10b; register 0x018[4] = 0b 1 the refin and refin self-bias points are offset slightly to avoid chatter on an open input condition. 2 for reliable operation of the digital lock detect, the period of the pfd frequency must be greater than the unlock-after-lock time.
ad9516-5 rev. a | page 6 of 76 clock inputs table 3. parameter min typ max unit test conditions/comments clock inputs (clk, clk ) differential input input frequency 0 1 2.4 ghz high frequency distribution (vco divider enabled) 0 1 1.6 ghz distribution only (vco divider bypassed; this is the frequency range supported by the channel divider) input sensitivity, differential 150 mv p-p measured at 2.4 ghz; jitter performance is improved with slew rates > 1 v/ns input level, differential 2 v p-p larger voltage swings may turn on the protection diodes and may degrade jitter performance input common-mode voltage, v cm 1.3 1.57 1.8 v self-biase d; enables ac coupling input common-mode range, v cmr 1.3 1.8 v with 200 mv p-p signal applied; dc-coupled input sensitivity, single-ended 150 mv p-p clk ac-coupled; clk ac-bypassed to rf ground input resistance 3.9 4.7 5.7 k self-biased input capacitance 2 pf 1 below about 1 mhz, the input should be dc-coupled. care should be taken to match v cm . clock outputs table 4. parameter min typ max unit test conditions/comments lvpecl clock outputs termination = 50 to v s_lvpecl ? 2 v out0, out1, out2, out3, out4, out5 differential (out, out ) output frequency, maximum 2400 mhz using direct to output; see figure 20 for peak-to- peak differential amplitude output high voltage (v oh ) v s_lvpecl ? 1.12 v s_lvpecl ? 0.98 v s_lvpecl ? 0.84 v measured at dc using the default amplitude setting; see figure 20 for amplitude vs. frequency output low voltage (v ol ) v s_lvpecl ? 2.03 v s_lvpecl ? 1.77 v s_lvpecl ? 1.49 v measured at dc using the default amplitude setting; see figure 20 for amplitude vs. frequency output differential voltage (v od ) 550 790 980 mv v oh ? v ol for each leg of a differential pair for default amplitude setting with driver not toggling; see figure 20 for variation over frequency lvds clock outputs differential termination 100 at 3.5 ma out6, out7, out8, out9 differential (out, out ) output frequency, maximum 800 mhz the ad9516 outputs can toggle at higher frequencies, but the output amplitude may not meet the v od specification; see figure 21 differential output voltage (v od ) 247 360 454 mv v oh ? v ol measurement across a differential pair at the default amplitude setting with output driver not toggling; see figure 21 for variation over frequency delta v od 25 mv this is the absolute value of the difference between v od when the normal output is high vs. when the complementary output is high output offset voltage (v os ) 1.125 1.24 1.375 v (v oh + v ol )/2 across a differential pair at the default amplitude setting with output driver not toggling delta v os 25 mv this is the absolute value of the difference between v os when the normal output is high vs. when the complementary output is high short-circuit current (i sa , i sb ) 14 24 ma output shorted to gnd cmos clock outputs out6a, out6b, out7a, out7b, out8a, out8b, out9a, out9b single-ended; termination = 10 pf output frequency 250 mhz see figure 22 output voltage high (v oh ) v s_lvpecl ? 0.1 v at 1 ma load output voltage low (v ol ) 0.1 v at 1 ma load
ad9516-5 rev. a | page 7 of 76 clock output additive phase noise (distribution only; vco divider not used) table 5. parameter min typ max unit test conditions/comments clk-to-lvpecl additive phase noise distri bution section only; do es not include pll input clk = 1 ghz, output = 1 ghz slew rate > 1 v/ns divider = 1 at 10 hz offset ?109 dbc/hz at 100 hz offset ?118 dbc/hz at 1 khz offset ?130 dbc/hz at 10 khz offset ?139 dbc/hz at 100 khz offset ?144 dbc/hz at 1 mhz offset ?146 dbc/hz at 10 mhz offset ?147 dbc/hz at 100 mhz offset ?149 dbc/hz clk = 1 ghz, output = 200 mhz input slew rate > 1 v/ns divider = 5 at 10 hz offset ?120 dbc/hz at 100 hz offset ?126 dbc/hz at 1 khz offset ?139 dbc/hz at 10 khz offset ?150 dbc/hz at 100 khz offset ?155 dbc/hz at 1 mhz offset ?157 dbc/hz >10 mhz offset ?157 dbc/hz clk-to-lvds additive phase noise distribution section only; does not include input slew clk = 1.6 ghz, output = 800 mhz rate > 1 v/ns divider = 2 at 10 hz offset ?103 dbc/hz at 100 hz offset ?110 dbc/hz at 1 khz offset ?120 dbc/hz at 10 khz offset ?127 dbc/hz at 100 khz offset ?133 dbc/hz at 1 mhz offset ?138 dbc/hz at 10 mhz offset ?147 dbc/hz at 100 mhz offset ?149 dbc/hz clk = 1.6 ghz, output = 400 mhz input slew rate > 1 v/ns divider = 4 at 10 hz offset ?114 dbc/hz at 100 hz offset ?122 dbc/hz at 1 khz offset ?132 dbc/hz at 10 khz offset ?140 dbc/hz at 100 khz offset ?146 dbc/hz at 1 mhz offset ?150 dbc/hz >10 mhz offset ?155 dbc/hz clk-to-cmos additive phase noise distrib ution section only; does not include pll input clk = 1 ghz, output = 250 mhz slew rate > 1 v/ns divider = 4 at 10 hz offset ?110 dbc/hz at 100 hz offset ?120 dbc/hz at 1 khz offset ?127 dbc/hz at 10 khz offset ?136 dbc/hz at 100 khz offset ?144 dbc/hz at 1 mhz offset ?147 dbc/hz >10 mhz offset ?154 dbc/hz
ad9516-5 rev. a | page 8 of 76 parameter min typ max unit test conditions/comments clk = 1 ghz, output = 50 mhz input slew rate > 1 v/ns divider = 20 at 10 hz offset ?124 dbc/hz at 100 hz offset ?134 dbc/hz at 1 khz offset ?142 dbc/hz at 10 khz offset ?151 dbc/hz at 100 khz offset ?157 dbc/hz at 1 mhz offset ?160 dbc/hz >10 mhz offset ?163 dbc/hz clock output absolute time jitter (clock generation using external vcxo) table 6. parameter min typ max unit test conditions/comments lvpecl output absolute time jitter application example based on a typical setup using an external 245.76 mhz vcxo (toyocom tco-2112); reference = 15.36 mhz; r = 1 lvpecl = 245.76 mhz; pll lbw = 125 hz 54 fs rms integration bandwidth = 200 khz to 5 mhz 77 fs rms integration bandwidth = 200 khz to 10 mhz 109 fs rms integration bandwidth = 12 khz to 20 mhz lvpecl = 122.88 mhz; pll lbw = 125 hz 79 fs rms integration bandwidth = 200 khz to 5 mhz 114 fs rms integration bandwidth = 200 khz to 10 mhz 163 fs rms integration bandwidth = 12 khz to 20 mhz lvpecl = 61.44 mhz; pll lbw = 125 hz 124 fs rms integration bandwidth = 200 khz to 5 mhz 176 fs rms integration bandwidth = 200 khz to 10 mhz 259 fs rms integration bandwidth = 12 khz to 20 mhz clock output additive time jitter (vco divider not used) table 7. parameter min typ max unit test conditions/comments lvpecl output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 622.08 mhz; lvpecl = 622.08 mhz; divider = 1 40 fs rms bandwidth = 12 khz to 20 mhz clk = 622.08 mhz; lvpecl = 155.52 mhz; divider = 4 80 fs rms bandwidth = 12 khz to 20 mhz clk = 1.6 ghz; lvpecl = 100 mhz; divider = 16 215 fs rms calculated from snr of adc method; dcc not used for even divides clk = 500 mhz; lvpecl = 100 mhz; divider = 5 245 fs rms calculated from snr of adc method; dcc on lvds output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 1.6 ghz; lvds = 800 mhz; divider = 2 (vco divider not used) 85 fs rms bandwidth = 12 khz to 20 mhz clk = 1 ghz; lvds = 200 mhz; divider = 5 113 fs rms bandwidth = 12 khz to 20 mhz clk = 1.6 ghz; lvds = 100 mhz; divider = 16 280 fs rms calculated from snr of adc method; dcc not used for even divides cmos output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 1.6 ghz; cmos = 100 mhz; divider = 16 365 fs rms calculated from snr of adc method; dcc not used for even divides
ad9516-5 rev. a | page 9 of 76 clock output additive time jitter (vco divider used) table 8. parameter min typ max unit test conditions/comments lvpecl output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 2.4 ghz; vco div = 2; lvpecl = 100 mhz; divider = 12; duty-cycle correction = off 210 fs rms calculated from snr of adc method lvds output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 2.4 ghz; vco div = 2; lvds = 100 mhz; divider = 12; duty-cycle correction = off 285 fs rms calculated from snr of adc method cmos output additive time jitter distribution section only; does not include pll; uses rising edge of clock signal clk = 2.4 ghz; vco div = 2; cmos = 100 mhz; divider = 12; duty-cycle correction = off 350 fs rms calculated from snr of adc method delay block additive time jitter table 9. parameter min typ max unit test conditions/comments delay block additive time jitter 1 incremental additive jitter 100 mhz output delay (1600 a, 0x1c) fine adjust 000000b 0.54 ps rms delay (1600 a, 0x1c) fine adjust 101111b 0.60 ps rms delay (800 a, 0x1c) fine adjust 000000b 0.65 ps rms delay (800 a, 0x1c) fine adjust 101111b 0.85 ps rms delay (800 a, 0x4c) fine adjust 000000b 0.79 ps rms delay (800 a, 0x4c) fine adjust 101111b 1.2 ps rms delay (400 a, 0x4c) fine adjust 000000b 1.2 ps rms delay (400 a, 0x4c) fine adjust 101111b 2.0 ps rms delay (200 a, 0x1c) fine adjust 000000b 1.3 ps rms delay (200 a, 0x1c) fine adjust 101111b 2.5 ps rms delay (200 a, 0x4c) fine adjust 000000b 1.9 ps rms delay (200 a, 0x4c) fine adjust 101111b 3.8 ps rms 1 this value is incremental; that is, it is in addition to the jitter of the lvds or cmos output without the delay. to estimate the total jitter, the lvds or cmos output jitter should be added to this value using the root sum of the squares (rss) method.
ad9516-5 rev. a | page 10 of 76 serial control port table 10. parameter min typ max unit test conditions/comments cs (input) cs has an internal 30 k pull-up resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 3 a input logic 0 current 110 a input capacitance 2 pf sclk (input) sclk has an internal 30 k pull-down resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 110 a input logic 0 current 1 a input capacitance 2 pf sdio (when input) input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 10 na input logic 0 current 20 na input capacitance 2 pf sdio, sdo (outputs) output logic 1 voltage 2.7 v output logic 0 voltage 0.4 v timing clock rate (sclk, 1/t sclk ) 25 mhz pulse width high, t high 16 ns pulse width low, t low 16 ns sdio to sclk setup, t ds 2 ns sclk to sdio hold, t dh 1.1 ns sclk to valid sdio and sdo, t dv 8 ns cs to sclk setup and hold, t s , t h 2 ns cs minimum pulse width high, t pwh 3 ns pd , reset , and sync pins table 11. parameter min typ max unit test conditions/comments input characteristics each of these pi ns has an internal 30 k pull-up resistor logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 110 a logic 0 current 1 a capacitance 2 pf reset timing pulse width low 50 ns sync timing pulse width low 1.5 high speed clock cycles high speed clock is clk input signal
ad9516-5 rev. a | page 11 of 76 ld, status, and refmon pins table 12. parameter min typ max unit test conditions/comments output characteristics when selected as a digital output (cmos); there are other modes in which these pins are not cmos digital outputs; see table 49 : register 0x017, register 0x01a, and register 0x01b output voltage high, v oh 2.7 v output voltage low, v ol 0.4 v maximum toggle rate 100 mhz applies when mux is set to any divider or counter output or pfd up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling analog lock detect capacitance 3 pf on-chip capacitance; used to calculate rc time constant for analog lock detect readback; use a pull-up resistor ref1, ref2, and clk frequency status monitor normal range 1.02 mhz frequency above which the monitor always indicates the presence of the reference extended range 8 khz frequency above which the monitor always indicates the presence of the reference ld pin comparator trip point 1.6 v hysteresis 260 mv power dissipation table 13. parameter min typ max unit test conditions/comments power dissipation, chip the values in this table include all power supplies, unless otherwise noted; the power deltas for individual drivers are at dc; see figure 7 , figure 8 , and figure 9 for power dissipation vs. output frequency power-on default 1.0 1.2 w no clock; no programming; defa ult register values; does not include power dissipated in external resistors; this configuration has the following blocks already powered up: vco divider, six channel dividers, three lvpecl drivers, and two lvds drivers full operation; cmos outputs at 225 mhz 1.5 2.1 w f clk = 2.25 ghz; vco divider = 2; all channel dividers on; six lvpecl outputs at 562.5 mhz; eight cmos outputs (10 pf load) at 225 mhz; all four fine delay blocks on, maximum current; does not include power dissipated in external resistors full operation; lvds outputs at 225 mhz 1.5 2.1 w f clk = 2.25 ghz; vco divider = 2; all channel dividers on; six lvpecl outputs at 562.5 mhz; fo ur lvds outputs at 225 mhz; all four fine delay blocks on: maximum current; does not include power dissipated in external resistors pd power-down 75 185 mw pd pin pulled low; does not include power dissipated in terminations pd power-down, maximum sleep 31 mw pd pin pulled low; pll power-down, register 0x010[1:0] = 01b; sync power-down, register 0x230[2] = 1b; ref for distribution power-down, register 0x230[1] = 1b v cp supply 4 4.8 mw pll operating; typical closed -loop configuration (this number is included in all other power measurements) ad9516 core 220 mw ad9516 core only, all drivers off, pll off, vco divider off, and delay blocks off; the power consumption of the configuration of the user can be derived from this number and the power deltas that follow
ad9516-5 rev. a | page 12 of 76 parameter min typ max unit test conditions/comments power deltas, individual functions power delta when a function is enabled/disabled vco divider 30 mw vco divider bypassed refin (differential) 20 mw all references off to differential reference enabled ref1, ref2 (single-ended) 4 mw all references off to ref1 or ref2 enabled; differential reference not enabled pll 75 mw pll off to pll on, normal operation; no reference enabled channel divider 30 mw divider bypassed to divide-by-2 to divide-by-32 lvpecl channel (divider plus output driver) 120 mw no lvpecl output on to one lvpecl output on (that is, enabling out0 with out1 off; divider 0 enabled), independent of frequency lvpecl driver 90 mw second lvpecl output turned on, same channel (that is, enabling out0 with out1 already on) lvds channel (divider plus output driver) 140 mw no lvds output on to one lvds output on (that is, enabling out8 with out9 off with divi der 4.1 enabled and divider 4.2 bypassed); see figure 8 for dependence on output frequency lvds driver 50 mw second lvds output turned on, same channel (that is, enabling out8 with out9 already on) cmos channel (divider plus output driver) 100 mw static; no cmos output on to one cmos output on (that is, enabling out8a starting with out8 and out9 off ); see figure 9 for variation over output frequency cmos driver (second in pair) 0 mw static; second cmos output, same pair, turned on (that is, enabling out8a with out8b already on) cmos driver (first in second pair) 30 mw static; first output, second pair, turned on (that is, enabling out9a with out9b off and out8a and out8b already on) fine delay block 50 mw delay block off to delay block enabled; maximum current setting
ad9516-5 rev. a | page 13 of 76 timing characteristics table 14. parameter min typ max unit test conditions/comments lvpecl termination = 50 to v s_lvpecl ? 2 v; default amplitude setting (810 mv) output rise time, t rp 70 180 ps 20% to 80%, measured differentially output fall time, t fp 70 180 ps 80% to 20%, measured differentially propagation delay, t pecl , clk-to-lvpecl output high frequency clock distribution configuration 835 995 1180 ps see figure 34 clock distribution configuration 773 933 1090 ps see figure 33 variation with temperature 0.8 ps/c output skew, lvpecl outputs 1 lvpecl outputs that share the same divider 5 15 ps lvpecl outputs on different dividers 13 40 ps all lvpecl outputs across multiple parts 220 ps lvds termination = 100 differential; 3.5 ma setting output rise time, t rl 170 350 ps 20% to 80%, measured differentially 2 output fall time, t fl 160 350 ps 20% to 80%, measured differentially 2 propagation delay, t lvds , clk-to-lvds output delay off on all outputs out6, out7, out8, out9 for all divide values 1.4 1.8 2.1 ns variation with temperature 1.25 ps/c output skew, lvds outputs 1 delay off on all outputs lvds outputs that share the same divider 6 62 ps lvds outputs on different dividers 25 150 ps all lvds outputs across multiple parts 430 ps cmos termination = open output rise time, t rc 495 1000 ps 20% to 80%; c load = 10 pf output fall time, t fc 475 985 ps 80% to 20%; c load = 10 pf propagation delay, t cmos , clk-to-cmos output fine delay off for all divide values 1.6 2.1 2.6 ns variation with temperature 2.6 ps/c output skew, cmos outputs 1 fine delay off cmos outputs that share the same divider 4 66 ps all cmos outputs on different dividers 28 180 ps all cmos outputs across multiple parts 675 ps delay adjust 3 lvds and cmos shortest delay range 4 register 0x0a1 (0x0a4, 0x0a7, 0x0aa), bits[5:0] = 101111b zero scale 50 315 680 ps register 0x0a2 (0x0a5, 0x0a8, 0x0ab), bits[5:0] = 000000b full scale 540 880 1180 ps register 0x0a2 (0x0a5, 0x0a8, 0x0ab), bits[5:0] = 101111b longest delay range 4 register 0x0a1 (0x0a4, 0x0a7, 0x0aa) bits[5:0] = 000000b zero scale 200 570 950 ps register 0x0a2 (0x0a5, 0x0a8, 0x0ab), bits[5:0] = 000000b quarter scale 1.72 2.31 2.89 ns register 0x0a2 (0x0a5, 0x0a8, 0x0ab), bits[5:0] = 001100b full scale 5.7 8.0 10.1 ns register 0x0a2 (0x0a5, 0x0a8, 0x0ab), bits[5:0] = 101111b delay variation with temperature short delay range 5 zero scale 0.23 ps/c full scale ?0.02 ps/c long delay range 5 zero scale 0.3 ps/c full scale 0.24 ps/c 1 this is the difference between any two similar delay pa ths while operating at the s ame voltage and temperature. 2 corresponding cmos drivers set to outxa for noninverting and outxb for inverting; x = 6, 7, 8, or 9. 3 the maximum delay that can be used is a little less than one-half the period of the clock. a longer delay disables the output. 4 incremental delay; does not include propagation delay. 5 all delays between zero scale and full scal e can be estimated by linear interpolation.
ad9516-5 rev. a | page 14 of 76 timing diagrams cl k t cmos t clk t lvds t pecl 07972-060 figure 2. clk/ clk to clock output timing, divider = 1 differential lvpecl 80% 20% t rp t fp 07972-061 figure 3. lvpecl timing, differential differential lvds 80% 20% t rl t fl 07972-062 figure 4. lvds timing, differential single-ended cmos 10pf load 80% 20% t rc t fc 07972-063 figure 5. cmos timing, si ngle-ended, 10 pf load
ad9516-5 rev. a | page 15 of 76 absolute maximum ratings table 15. parameter rating vs, vs_lvpecl to gnd ?0.3 v to +3.6 v vcp to gnd ?0.3 v to +5.8 v refin, refin to gnd ?0.3 v to vs + 0.3 v refin to refin ?3.3 v to +3.3 v rset to gnd ?0.3 v to vs + 0.3 v cprset to gnd ?0.3 v to vs + 0.3 v clk, clk to gnd ?0.3 v to vs + 0.3 v clk to clk ?1.2 v to +1.2 v sclk, sdio, sdo, cs to gnd ?0.3 v to vs + 0.3 v out0, out0 , out1, out1 , out2, out2 , out3, out3 , out4, out4 , out5, out5 , out6, out6 , out7, out7 , out8, out8 , out9, out9 to gnd ?0.3 v to vs + 0.3 v sync to gnd ?0.3 v to vs + 0.3 v refmon, status, ld to gnd ?0.3 v to vs + 0.3 v temperature junction temperature 1 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c 1 see table 16 for ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 16. package type 1 ja unit 64-lead lfcsp (cp-64-4) 22 c/w 1 thermal impedance measurem ents were taken on a 4- layer board in still air in accordance with eia/jesd51-2. esd caution
ad9516-5 rev. a | page 16 of 76 pin configuration and fu nction descriptions pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cs nc nc nc sdo sdio reset pd out4 out4 vs_lvpecl out5 out5 vs vs vs 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 refin (ref1) refin (ref2) cprset vs vs gnd rset vs out0 out0 vs_lvpecl out1 out1 vs vs vs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vs refmon ld vcp cp status ref_sel sync nc nc vs vs clk clk nc sclk out6 (out6a) out6 (out6b) out7 (out7a) out7 (out7b) gnd out2 out2 vs_lvpecl out3 out3 vs gnd out9 (out9b) out9 (out9a) out8 (out8b) out8 (out8a) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad9516-5 top view (not to scale) lvpecl lvpecl lvpecl lvpecl lvpecl lvpecl lvds/cmos w/fine delay adjust lvds/cmos w/fine delay adjust notes 1. nc = no connect. do not connect to this pin. 2. exposed die pad must be connected to gnd. 07972-003 figure 6. pin configuration table 17. pin function descriptions pin no. input/ output pin type mnemonic description 1, 11, 12, 30, 31, 32, 38, 49, 50, 51, 57, 60, 61 i power vs 3.3 v power pins. 2 o 3.3 v cmos refmon reference monitor (output). this pin has multiple selectable outputs; see table 49 , register 0x01b. 3 o 3.3 v cmos ld lock detect (output). this pin has multiple selectable outputs; see table 49 , register 0x01a. 4 i power vcp power supply for charge pump (cp); vs vcp 5.25 v. 5 o loop filter cp charge pump (output). this pin connects to an external loop filter. this pin can be left unconnected if the pll is not used. 6 o 3.3 v cmos status status (output). this pin has mu ltiple selectable outputs; see table 49 , register 0x017. 7 i 3.3 v cmos ref_sel reference select. selects ref1 (low) or ref2 (high). this pin has an internal 30 k pull-down resistor. 8 i 3.3 v cmos sync manual synchronizations and manual ho ldover. this pin initiates a manual synchronization and is also used for manual holdover. active low. this pin has an internal 30 k pull-up resistor. 9, 10, 15, 18, 19, 20 n/a nc nc no connection. these pins can be left floating. along with clk , this is the differential input fo r the clock distribution section. 13 i differential clock input clk 14 i differential clock input clk along with clk, this is the differential input for the clock distribution section. if a single-ended input is connected to the clk pin, connect a 0.1 f bypass capacitor from clk to ground.
ad9516-5 rev. a | page 17 of 76 pin no. input/ output pin type mnemonic description 16 i 3.3 v cmos sclk serial control port data clock signal. 17 i 3.3 v cmos cs serial control port chip select; active low. this pin has an internal 30 k pull-up resistor. 21 o 3.3 v cmos sdo serial control port unidirectional se rial data output. 22 i/o 3.3 v cmos sdio serial control port bidirectional serial data input/output. 23 i 3.3 v cmos reset chip reset; active low. this pin has an internal 30 k pull-up resistor. 24 i 3.3 v cmos pd chip power-down; active low. this pin has an internal 30 k pull-up resistor. 25 o lvpecl out4 lvpecl output; one side of a differential lvpecl output. 26 o lvpecl out4 lvpecl output; one side of a differential lvpecl output. 27, 41, 54 i power vs_lvpecl extended voltage 2.5 v to 3.3 v lvpecl power pins. 28 o lvpecl out5 lvpecl output; one side of a differential lvpecl output. 29 o lvpecl out5 lvpecl output; one side of a differential lvpecl output. 33 o lvds or cmos out8 (out8a) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 34 o lvds or cmos out8 (out8b) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 35 o lvds or cmos out9 (out9a) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 36 o lvds or cmos out9 (out9b) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 37, 44, 59, epad i gnd gnd ground pins, including external paddle (epad). the external die paddle on the bottom of the package must be connect ed to ground for proper operation. 39 o lvpecl out3 lvpecl output; one side of a differential lvpecl output. 40 o lvpecl out3 lvpecl output; one side of a differential lvpecl output. 42 o lvpecl out2 lvpecl output; one side of a differential lvpecl output. 43 o lvpecl out2 lvpecl output; one side of a differential lvpecl output. 45 o lvds or cmos out7 (out7b) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 46 o lvds or cmos out7 (out7a) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 47 o lvds or cmos out6 (out6b) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 48 o lvds or cmos out6 (out6a) lvds/cmos output; one side of a differential lvds output, or a single-ended cmos output. 52 o lvpecl out1 lvpecl output; one side of a differential lvpecl output. 53 o lvpecl out1 lvpecl output; one side of a differential lvpecl output. 55 o lvpecl out0 lvpecl output; one side of a differential lvpecl output. 56 o lvpecl out0 lvpecl output; one side of a differential lvpecl output. 58 o current set resistor rset a resistor connected to this pin sets internal bias currents. nominal value = 4.12 k. 62 o current set resistor cprset a resistor connected to this pin sets the cp current range. nominal value = 5.1 k. this resistor can be omitted if the pll is not used. 63 i reference input refin (ref2) along with refin, this pin is th e differential input for the pll reference. alternatively, this pin is a single-ended input for ref2. this pin can be left unconnected when the pll is not used. 64 i reference input refin (ref1) along with refin , this pin is the differential input for the pll reference. alternatively, this pin is a single-ended input for ref1. this pin can be left unconnected when the pll is not used.
ad9516-5 rev. a | page 18 of 76 typical performance characteristics 300 100 120 140 160 180 200 220 240 260 280 0 500 1000 1500 2000 2500 3000 current (ma) frequency (mhz) 3 channels?6 lvpecl 3 channels?3 lvpecl 2 channels?2 lvpecl 1 channel?1 lvpecl 07972-007 figure 7. current vs. frequency, direct to output, lvpecl outputs 180 160 140 120 100 80 0 200 400 600 800 current (ma) frequency (mhz) 1 channel?1 lvds 2 channels?2 lvds 2 channels?4 lvds 07972-008 figure 8. current vs. frequencylvds outputs (includes clock distribution current draw) 240 200 160 220 180 140 120 100 80 02 200 150 100 50 current (ma) frequency (mhz) 5 0 1 channel?2 cmos 1 channel?1 cmos 2 channels?2 cmos 2 channels?8 cmos 07972-009 figure 9. current vs. frequency cmos outputs with 10 pf load 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 current from cp pin (ma) voltage on cp pin (v) pump down pump up 07972-011 figure 10. charge pump characteristics at vcp = 3.3 v 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 3.0 4.0 2.5 3.5 5.04.5 current from cp pin (ma) voltage on cp pin (v) pump down pump up 07972-012 figure 11. charge pump characteristics at v cp = 5.0 v ? 140 ?145 ?150 ?155 ?160 ?165 ?170 0.1 1 100 10 pfd phase noise referred to pfd input (dbc/hz) pfd frequency (mhz) 07972-013 figure 12. pfd phase noise referred to pfd input vs. pfd frequency
ad9516-5 rev. a | page 19 of 76 ? 210 ?224 ?222 ?220 ?218 ?216 ?214 ?212 02 2.0 1.5 1.0 0.5 pll figure of merit (dbc/hz) slew rate (v/ns) . 5 07972-136 figure 13. pll figure of me rit vs. slew rate at refin/ refin 1.0 0.6 0.2 ?0.2 ?0.6 ?1.0 02 20 15 10 5 differential output (v) time (ns) 5 07972-014 figure 14. lvpecl output (differential) at 100 mhz 1.0 0.6 0.2 ?0.2 ?0.6 ?1.0 02 1 differential output (v) time (ns) 07972-015 figure 15. lvpecl output (differential) at 1600 mhz 0.4 0.2 0 ?0.2 ?0.4 02 20 15 10 5 differential output (v) time (ns) 5 07972-016 figure 16. lvds output (differential) at 100 mhz 0.4 0.2 0 ?0.2 ?0.4 02 1 differential output (v) time (ns) 07972-017 figure 17. lvds output (differential) at 800 mhz 2.8 0.8 1.8 ?0.2 08 60 100 40 20 differential output (v) time (ns) 0 07972-018 figure 18. cmos output at 25 mhz
ad9516-5 rev. a | page 20 of 76 2 2.8 0.8 1.8 ?0.2 08 61 10 4 2 output (v) time (ns) 07972-019 figure 19. cmos output at 250 mhz 1600 800 1000 1200 1400 03 2 1 differential swing (mv p-p) frequency (ghz) 07972-020 figure 20. lvpecl differential swing vs. frequency (using a differential probe across the output pair) 700 500 600 08 700 600 500 400 300 200 100 differential swing (mv p-p) frequency (mhz) 0 0 07972-021 figure 21. lvds differential swing vs. frequency (using a differential probe across the output pair) 3 2 1 0 0 600 500 400 300 200 100 output swing (v) output frequency (mhz) c l = 2pf c l = 10pf c l = 20pf 07972-133 figure 22. cmos output swing vs . frequency and capacitive load
ad9516-5 rev. a | page 21 of 76 ? 120 ?130 ?125 ?135 ?140 ?145 ?150 ?155 ?160 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) 07972-026 figure 23. phase noise (additive) lv pecl at 245.76 mhz, divide-by-1 ? 110 ?120 ?130 ?140 ?150 ?160 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) 07972-027 figure 24. phase noise (additive) lvpecl at 200 mhz, divide-by-5 ? 100 ?110 ?120 ?130 ?140 ?150 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) 07972-128 figure 25. phase noise (additive) lv pecl at 1600 mhz, divide-by-1 ? 110 ?160 ?150 ?140 ?130 ?120 10 100m 1k 10k 100k 1m 10m 100 phase noise (dbc/hz) frequency (hz) 07972-142 figure 26. phase noise (additive) lvds at 200 mhz, divide-by-1 ? 100 ?110 ?120 ?130 ?140 ?150 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) 07972-130 figure 27. phase noise (additive) lvds at 800 mhz, divide-by-2 ? 120 ?130 ?140 ?150 ?160 ?170 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) 07972-131 figure 28. phase noise (additive ) cmos at 50 mhz, divide-by-20
ad9516-5 rev. a | page 22 of 76 ? 100 ?110 ?120 ?130 ?140 ?150 ?160 10 100m 10m 1m 100k 10k 1k 100 phase noise (dbc/hz) frequency (hz) 07972-132 figure 29. phase noise (additive) cmos at 250 mhz, divide-by-4 ? 120 ?160 ?150 ?140 ?130 1k 100m 10m 1m 100k 10k phase noise (dbc/hz) frequency (hz) 07972-140 figure 30. phase noise (absolute), external vcxo (toyocom tco-2112) at 245.76 mhz; pfd = 15.36 mhz; lbw = 250 hz; lvpecl output = 245.76 mhz 1000 100 10 1 0.1 0.01 0.1 1 10 100 1000 input jitter amplitude (ui p-p) jitter frequency (khz) 07972-148 oc-48 objective mask ad9516 note: 375ui max at 10hz offset is the maximum jitter that can be generated by the test equipment. failure point is greater than 375ui. f obj figure 31. gr-253 jitter tolerance plot
ad9516-5 rev. a | page 23 of 76 terminology phase jitter and phase noise an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in decibels, db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. it is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs, dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal-to-noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given converter. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted. this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9516-5 rev. a | page 24 of 76 detailed block diagram programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 ad9516-5 status status r divider vco status programmable r delay reference switchover ref_ sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 out4 out5 out4 out5 lvpecl divide by 1 to 32 divide by 1 to 32 lvds/cmos ? t ? t divide by 1 to 32 divide by 1 to 32 lvds/cmos ? t ? t divide by 1 to 32 01 divide by 2, 3, 4, 5, or 6 pd sync reset sclk sdio sdo cs digital logic serial control port out6 (out6a) out6 (out6b) out7 (out7a) out7 (out7b) out8 (out8a) out8 (out8b) out9 (out9a) out9 (out9b) 0 7972-002 figure 32. detailed block diagram
ad9516-5 rev. a | page 25 of 76 theory of operation programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 ad9516-5 status status r divider vco status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 out4 out5 out4 out5 lvpecl divide by 1 to 32 divide by 1 to 32 lvds/cmos out6 (out6a) out6 (out6b) ? t out7 (out7a) out7 (out7b) ? t divide by 1 to 32 divide by 1 to 32 lvds/cmos out8 (out8a) out8 (out8b) ? t out9 (out9a) out9 (out9b) ? t divide by 1 to 32 01 divide by 2, 3, 4, 5, or 6 pd sync reset sclk sdio sdo cs digital logic serial control port 07972-028 figure 33. clock distribution or external vco < 1600 mhz (mode 1) operational configurations the ad9516 can be configured in several ways. these configurations must be set up by loading the control registers (see table 47 and table 48 through tabl e 57 ). each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. mode 1clock distribution or external vco < 1600 mhz mode 1 bypasses the vco divider. mode 1 can be used only with an external clock source of <1600 mhz, due to the maximum input frequency allowed at the channel dividers. for clock distribution applications where the external clock is less than 1600 mhz, use the register settings shown in table 18 . table 18. settings for clock distribution < 1600 mhz register description 0x010[1:0] = 01b pll asynchronous power-down (pll off ) 0x1e1[0] = 1b bypass the vco divider as source for distribution section when using the internal pll with an external vco of <1600 mhz, the pll must be turned on.
ad9516-5 rev. a | page 26 of 76 table 19. settings for using an internal pll with an external vco < 1600 mhz register description 0x1e1[0] = 1b bypass the vco divider as source for distribution section 0x010[1:0] = 00b pll normal operation (pll on) along with other appropriate pll settings in register 0x010 to register 0x01e an external vco/vcxo requires an external loop filter that must be connected between cp and the tuning pin of the vco/ vcxo. this loop filter determines the loop bandwidth and stability of the pll. ensure that the correct pfd polarity is selected for the vco/vcxo that is being used. table 20. setting the pfd polarity register description 0x010[7] = 0b pfd polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b pfd polarity negative (higher control voltage produces lower frequency) after the appropriate register values are programmed, register 0x232 must be set to 0x01 for the values to take effect. mode 2 (high frequency clock distribution)clk or external vco > 1600 mhz the ad9516 power-up default configuration has the pll powered off and the routing of the input set so that the clk/ clk input is connected to the distribution section through the vco divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/ divide-by-6). this is a distribution-only mode that allows for an external input of up to 2400 mhz (see table 4). for divide ratios other than 1, the maximum frequency that can be applied to the channel dividers is 1600 mhz. therefore, the vco divider must be used to divide down input frequencies that are greater than 1600 mhz before the channel dividers can be used for further division. this input routing can also be used for lower input frequencies, but the minimum divide is 2 before the channel dividers. when the pll is enabled, this routing also allows the use of the pll with an external vco or vcxo with a frequency of <2400 mhz. in this configuration, the external vco/vcxo feeds directly into the prescaler. the register settings shown in table 21 are the default values of these registers at power-up or after a reset operation. if the contents of the registers are altered by prior programming after power-up or reset, these registers can also be set intentionally to these values. table 21. default settings of some pll registers register description 0x010[1:0] = 01b pll asynchronous power-down (pll off ). 0x1e0[2:0] = 010b set vco divider = 4. 0x1e1[0] = 0b use the vco divider. when using the internal pll with an external vco, the pll must be turned on. table 22. settings when using an external vco register description 0x010[1:0] = 00b pll normal operation (pll on). 0x010 to 0x01d pll settings. select and enable a reference input. set r, n (p, a, b), pfd polarity, and i cp according to the intended loop configuration. 0x1e1[1] = 0b clk selected as the source. an external vco requires an external loop filter that must be connected between cp and the tuning pin of the vco. this loop filter determines the loop bandwidth and stability of the pll. ensure that the correct pfd polarity is selected for the vco that is being used. table 23. setting the pfd polarity register description 0x010[7] = 0b pfd polarity positive (higher control voltage produces higher frequency). 0x010[7] = 1b pfd polarity negative (higher control voltage produces lower frequency). after the appropriate register values are programmed, register 0x232 must be set to 0x01 for the values to take effect.
ad9516-5 rev. a | page 27 of 76 programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 ad9516-5 status status r divider vco status programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold out0 out1 out0 out1 lvpecl divide by 1 to 32 out2 out3 out2 out3 lvpecl divide by 1 to 32 out4 out5 out4 out5 lvpecl divide by 1 to 32 divide by 1 to 32 lvds/cmos out6 (out6a) out6 (out6b) ? t out7 (out7a) out7 (out7b) ? t divide by 1 to 32 divide by 1 to 32 lvds/cmos out8 (out8a) out8 (out8b) ? t out9 (out9a) out9 (out9b) ? t divide by 1 to 32 01 divide by 2, 3, 4, 5, or 6 pd sync reset sclk sdio sdo cs digital logic serial control port 07972-029 figure 34. high frequency clock distributionclk or external vco > 1600 mhz (mode 2)
ad9516-5 rev. a | page 28 of 76 phase-locked loop (pll) clk charge pump r divider cp v cp v sgnd status cprset dist ref rset divide by 2, 3, 4, 5, or 6 a/b counters ld n divider refmon 01 0 1 p, p + 1 prescaler ref2 ref1 reference switchover hold vco status ref_sel lock detect status status clk phase frequency detector programmable n delay programmable r delay pll ref refin (ref1) refin (ref2) 07972-064 figure 35. pll functional blocks the ad9516 includes on-chip pll blocks that can be used with an external vco or vcxo to create a complete phase-locked loop. the pll requires an external loop filter, which usually consists of a small number of capacitors and resistors. the configuration and components of the loop filter help to establish the loop bandwidth and stability of the pll. the ad9516 pll is useful for generating clock frequencies from a supplied reference frequency. this includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution. in addition, the pll can be exploited to clean up jitter and phase noise on a noisy reference. the exact choices of pll parameters and loop dynamics are very application specific. the flexibility and depth of the pll allow the part to be tailored to function in many different applications and signal environments. configuration of the pll configuration of the pll is accomplished by programming the various settings for the r divider, n divider, pfd polarity, and charge pump current. the combination of these settings determines the pll loop bandwidth. these are managed through programmable register settings (see table 47 and table 49 ) and by the design of the external loop filter. successful pll operation and satisfactory pll loop performance are highly dependent upon proper configuration of the pll settings. the design of the external loop filter is crucial to the proper operation of the pll. a thorough knowledge of pll theory and design is helpful. adisimclk ? (v1.2 or later) is a free program that can help with the design and exploration of the capabilities and features of the ad9516 , including the design of the pll loop filter. it is available at www.analog.com/clocks . phase frequency detector (pfd) the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. the antibacklash pulse width is set by register 0x017[1:0]. an important limit to keep in mind is the maximum frequency allowed into the pfd, which, in turn, determines the correct anti- backlash pulse setting. the antibacklash pulse setting is specified in the phase/frequency detector (pfd) parameter of table 2 . charge pump (cp) the charge pump is controlled by the pfd. the pfd monitors the phase and frequency relationship between its two inputs, and tells the cp to pump up or pump down to charge or discharge the integrating node (part of the loop filter). the integrated and filtered cp current is transformed into a voltage that drives the tuning node of the external vco to move the vco frequency up or down. the cp can be set (via register 0x010[6:4]) for high impedance (allows holdover operation), for normal operation (attempts to lock the pll loop), for pump-up, or for pump-down (test modes). the cp current is programmable in eight steps from (nominally) 600 a to 4.8 ma. the exact value of the cp current lsb is set by the cprset resistor, which is nominally 5.1 k. if the value of the resistor connected to the cp_rset pin is doubled, the resulting charge pump current range becomes 300 a to 2.4 ma.
ad9516-5 rev. a | page 29 of 76 pll external loop filter an example of an external loop filter for a pll is shown in figure 36 . a loop filter must be calculated for each desired pll configuration. the values of the components depend on the vco frequency, the k vco , the pfd frequency, the charge pump current, the desired loop bandwidth, and the desired phase margin. the loop filter affects the phase noise, loop settling time, and loop stability. a basic knowledge of pll theory is helpful for under- standing loop filter design. adisimclk can help with calculation of a loop filter according to the application requirements. clk/clk external vco/vcxo charge pump cp c1 c2 c3 r1 r2 ad9516-5 07972-065 figure 36. example of external loop filter for pll pll reference inputs the ad9516 features a flexible pll reference input circuit that allows a fully differential input or two separate single-ended inputs. the input frequency range for the reference inputs is specified in table 2 . both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals. the differential input and the single-ended inputs share two pins, refin (ref1) and refin (ref2). the desired reference input type is selected and controlled by register 0x01c (see and ). table 47 table 49 when the differential reference input is selected, the self-bias level of the two sides is offset slightly (see table 2 ) to prevent chattering of the input buffer when the reference is slow or missing. the specification for this voltage level is found in table 2 . the input hysteresis increases the voltage swing required of the driver to overcome the offset. the differential reference input can be driven by either ac-coupled lvds or ac-coupled lvpecl signals. the single-ended inputs can be driven by either a dc-coupled cmos level signal or an ac-coupled sine wave or square wave. each single-ended input can be independently powered down when not needed to increase isolation and reduce power. either a differential or a single-ended reference must be specifically enabled. all pll reference inputs are off by default. the differential reference input is powered down whenever the pll is powered down, or when the differential reference input is not selected. the single-ended buffers power down when the pll is powered down and when their individual power-down registers are set. when the differential mode is selected, the single-ended inputs are powered down. in differential mode, the reference input pins are internally self- biased so that they can be ac-coupled via capacitors. it is possible to dc couple to these inputs. if the differential refin is driven by a single-ended signal, the unused side ( refin ) should be decoupled via a suitable capacitor to a quiet ground. shows the equivalent circuit of refin. figure 37 v s ref1 ref2 refin 150? 150? 10k ? 12k ? 10k ? 10k ? refin 85k ? v s 85k ? v s 07972-066 figure 37. refin eq uivalent circuit reference switchover the ad9516 supports dual single-ended cmos inputs, as well as a single differential reference input. in dual single-ended reference mode, automatic and manual pll reference clock switching between ref1 (pin refin) and ref2 (pin refin ) is supported. this feature supports networking and other applications that require smooth switching of redundant references. when used in conjunction with the automatic holdover function, the can achieve a worst-case reference input switchover with an output frequency disturbance as low as 10 ppm. ad9516 when using reference switchover, the single-ended reference inputs should be dc-coupled cmos levels that are never allowed to go to high impedance. if the inputs are allowed to go to high impedance, noise may cause the buffer to chatter, causing false detection of the presence of a reference. reference switchover can be performed manually or automatically. manual switchover is performed either through register 0x01c or by using the ref_sel pin. manual switchover requires the presence of a clock on the reference input that is being switched to, or that the deglitching feature be disabled (register 0x01c[7]). the reference switching logic fails if this condition is not met, and the pll does not reacquire.
ad9516-5 rev. a | page 30 of 76 automatic revertive switchover relies on the refmon pin to indicate when ref1 disappears. by programming register 0x01b = 0xf7 and register 0x01c = 0x26, the refmon pin is programmed to be high when ref1 is invalid, which commands the switch to ref2. when ref1 is valid again, the refmon pin goes low, and the part again locks to ref1. the status pin can also be used for this function, and ref2 can be used as the preferred reference. a switchover deglitch feature ensures that the pll does not receive rising edges that are far out of alignment with the newly selected reference. automatic nonrevertive switching is not supported. reference divider r the reference inputs are routed to the reference divider, r. r (a 14-bit counter) can be set to any value from 0 to 16,383 by writing to register 0x011 and register 0x012. (both r = 0 and r = 1 give divide-by-1.) the output of the r divider goes to one of the pfd inputs to be compared with the vco frequency divided by the n divider. the frequency applied to the pfd must not exceed the maximum allowable frequency, which depends on the antibacklash pulse setting (see tabl e 2 ). the r counter has its own reset. the r counter can be reset via the shared reset bit of the r, a, and b counters. it can also be reset by a sync operation. vcxo/vco feedback divider np, a, b the n divider is a combination of a prescaler (p) and two counters, a and b. the total divider value is n = ( p b ) + a where p can be 2, 4, 8, 16, or 32. prescaler the prescaler of the ad9516 allows for two modes of operation: a fixed divide (fd) mode of 1, 2, or 3, and a dual modulus (dm) mode where the prescaler divides by p and (p + 1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. the prescaler modes of operation are given in table 49 , register 0x016[2:0]. not all modes are available at all frequencies (see tabl e 2 ). when operating the ad9516 in dual modulus mode, p/(p + 1), the equation used to relate the input reference frequency to the vco output frequency is f vco = ( f ref / r ) ( p b + a ) = f ref n / r however, when operating the prescaler in fd mode 1, fd mode 2, or fd mode 3, the a counter is not used (a = 0) and the equation simplifies to f vco = ( f ref / r ) ( p b ) = f ref n / r when a = 0, the divide is a fixed divide of p = 2, 4, 8, 16, or 32, in which case, the previous equation also applies. by using combinations of dm and fd modes, the ad9516 can achieve values of n all the way down to n = 1 and up to n = 26,2175. table 2 4 shows how a 10 mhz reference input can be locked to any integer multiple of n. table 24. using a 10 mhz reference to generate different vco frequencies f ref (mhz) r p a b n f vco (mhz) mode conditions/comments 10 1 1 x 1 1 1 10 fd p = 1, b = 1 (a and b counters are bypassed). 10 1 2 x 1 1 2 20 fd p = 2, b = 1 (a and b counters are bypassed). 10 1 1 x 1 3 3 30 fd a counter is bypassed. 10 1 1 x 1 4 4 40 fd a counter is bypassed. 10 1 1 x 1 5 5 50 fd a counter is bypassed. 10 1 2 x 1 3 6 60 fd a counter is bypassed. 10 1 2 0 3 6 60 dm 10 1 2 1 3 7 70 dm maximum frequency into prescaler in p = 2/3 mode is 200 mhz. if n = 7 or n = 11 is desired for prescaler input frequency of 200 mhz to 300 mhz, use p = 1, and n = 7 or 11, respectively. 10 1 2 2 3 8 80 dm 10 1 2 1 4 9 90 dm 10 1 8 6 18 150 1500 dm 10 1 8 7 18 151 1510 dm 10 1 16 7 9 151 1510 dm 10 10 32 6 47 1510 1510 dm 10 1 8 0 25 200 2000 dm 10 1 16 14 16 270 2700 dm p = 8 is not allowed (2700 8 > 300 mhz). p = 32 is not allowed (a > b not allowed). 10 10 32 22 84 2710 2710 dm p = 32, a = 22, b = 84. p = 16 is also permitted. 1 x = dont care.
ad9516-5 rev. a | page 31 of 76 note that the same value of n can be derived in different ways, as illustrated by the case of n = 12. the user can choose a fixed divide mode of p = 2 with b = 6; use the dual modulus mode of 2/3 with a = 0, b = 6; or use the dual modulus mode of 4/5 with a = 0, b = 3. a and b counters the b counter must be 3 or bypassed, and, unlike the r counter, a = 0 is actually zero. when the prescaler is in dual modulus mode, the a counter must be less than the b counter. the maximum input frequency to the a or b counter is reflected in the maximum prescaler output frequency (~300 mhz) that is specified in table 2 . this is the prescaler input frequency (external vco or clk) divided by p. for example, a dual modulus mode of p = 8/9 mode is not allowed if the external vco frequency is greater than 2400 mhz because the frequency going to the a or b counter is too high. when the b counter is bypassed (b = 1), the a counter should be set to 0, and the overall resulting divide is equal to the prescaler setting, p. the possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. this mode is useful only when an external vco/vcxo is used because the frequency range of the internal vco requires an overall feedback divider that is greater than 32. although manual reset is not normally required, the a and b counters have their own reset bit. alternatively, the a and b counters can be reset using the shared reset bit of the r, a, and b counters. note that these reset bits are not self-clearing. r, a, and b counters sync pin reset the r, a, and b counters can also be reset simultaneously via the sync pin. this function is controlled by register 0x019[7:6] (see ). the table 49 sync pin reset is disabled by default. r and n divider delays both the r and n dividers feature a programmable delay cell. these delays can be enabled to allow adjustment of the phase relationship between the pll reference clock and the vco or clk. each delay is controlled by three bits. the total delay range is about 1 ns. see register 0x019 in table 49 . lock detect digital lock detect (dld) by selecting the proper output through the mux on each pin, the dld function can be made available at the ld, status, and refmon pins. the dld circuit indicates a lock when the time difference of the rising edges at the pfd inputs is less than a specified value (the lock threshold). the loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold). note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the lock window to occur without chattering on the lock indicator. the lock detect window timing depends on three settings: the digital lock detect window bit (register 0x018[4]), the antibacklash pulse width setting (register 0x017[1:0]), see table 2 ), and the lock detect counter (register 0x018[6:5]). a lock is not indicated until there is a programmable number of consecutive pfd cycles with a time difference that is less than the lock detect threshold. the lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle. for the lock detect to work properly, the period of the pfd frequency must be greater than the unlock threshold. the number of consecutive pfd cycles required for lock is programmable (register 0x018[6:5]). a nalog lock detect (ald) the ad9516 provides an ald function that can be selected for use at the ld pin. there are two versions of ald, as follows: ? n-channel open-drain lock detect. this signal requires a pull-up resistor to the positive supply, vs. the output is normally high with short, low going pulses. lock is indicated by the minimum duty cycle of the low going pulses. ? p-channel open-drain lock detect. this signal requires a pull-down resistor to gnd. the output is normally low with short, high going pulses. lock is indicated by the minimum duty cycle of the high going pulses. the analog lock detect function requires an r-c filter to provide a logic level indicating lock/unlock. ad9516-5 ald ld r1 c v out r2 v s = 3.3v 07972-067 figure 38. example of analog lock detect filter, using n-channel open-drain driver current source digital lock detect (csdld) during the pll locking sequence, it is normal for the dld signal to toggle a number of times before remaining steady when the pll is completely locked and stable. there may be applications where it is desirable to have dld asserted only after the pll is solidly locked. this is made possible by using the current source lock detect function. this function is set when it is selected as the output from the ld pin control (register 0x01a[5:0]). the current source lock detect provides a current of 110 a when dld is true, and it shorts to ground when dld is false. if a capacitor is connected to the ld pin, it charges at a rate that is determined by the current source during the dld true time but is discharged nearly instantly when dld is false. by monitoring the voltage at the ld pin (top of the capacitor), it is possible to get a logic high level only after the dld has been true for a sufficiently long time. any momentary dld false resets the charging. by selecting a properly sized capacitor, it is possible to delay a lock detect indication until the pll is locked in a stable condition and the lock detect does not chatter.
ad9516-5 rev. a | page 32 of 76 the voltage on the capacitor can be sensed by an external comparator connected to the ld pin. however, there is an internal ld pin comparator that can be read at the refmon pin control (register 0x01b[4:0]) or the status pin control (register 0x017[7:2]) as an active high signal. it is also available as an active low signal (refmon, register 0x01b[4:0] and status, register 0x017[7:2]). the internal ld pin comparator trip point and hysteresis are listed in table 12 . ad9516-5 ld refmon or status c v out 110a dld ld pin comparator 07972-068 figure 39. current source lock detect external vcxo/vco clock input (clk/ clk ) clk is a differential input that can be used to drive the ad9516 clock distribution section. this input can receive up to 2.4 ghz. the pins are internally self-biased, and the input signal should be ac-coupled via capacitors. vs clock input stage c lk c lk 5k? 5k? 2.5k ? 2.5k ? 07972-032 figure 40. clk equivalent input circuit the clk/ clk input can be used either as a distribution only input (with the pll off), or as a feedback input for an external vco/vcxo using the pll. the clk/ clk input can be used for frequencies up to 2.4 ghz. holdover the ad9516 pll has a holdover function. holdover is implemented by putting the charge pump into a high impedance state. this is useful when the pll reference clock is lost. holdover mode allows the vco to maintain a relatively constant frequency even though there is no reference clock. without this function, the charge pump is placed into a constant pump-up or pump- down state, resulting in a large vco frequency shift. because the charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the vco tuning node causes a drift of the vco frequency. this can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate (i leak /c) of the vco control voltage. for most applications, the frequency is sufficient for 3 sec to 5 sec. both a manual holdover mode, using the sync pin, and an automatic holdover mode are provided. to use either function, the holdover function must be enabled (register 0x01d[0] and register 0x01d[2]). manual holdover mode a manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the sync pin is asserted low. this operation is edge sensitive, not level sensitive. the charge pump enters a high impedance state immediately. to take the charge pump out of a high impedance state, take the sync pin high. the charge pump then leaves the high impedance state synchronously with the next pfd rising edge from the reference clock. this prevents extraneous charge pump events from occurring during the time between sync going high and the next pfd event. this also means that the charge pump stays in a high impedance state as long as there is no reference clock present. the b counter (in the n divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path pfd event. this helps align the edges out of the r and n dividers for faster settling of the pll. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out. when using this mode, set the channel dividers to ignore the sync pin (at least after an initial sync event). if the dividers are not set to ignore the sync pin, the distribution outputs turn off each time sync is taken low to put the part into holdover.
ad9516-5 rev. a | page 33 of 76 automatic/internal holdover mode when enabled, this function automatically puts the charge pump into a high impedance state when the loop loses lock. the assumption is that the only reason that the loop loses lock is due to the pll losing the reference clock; therefore, the holdover function puts the charge pump into a high impedance state to maintain the vco frequency as close as possible to the original frequency before the reference clock disappears. see figure 41 for a flowchart of the internal/automatic holdover function operation. the holdover function senses the logic level of the ld pin as a condition to enter holdover. the signal at ld can be from the dld, ald, or current source ld (csdld) mode. it is possible to disable the ld comparator (register 0x01d[3]), which causes the holdover function to always sense ld as high. if dld is used, it is possible for the dld signal to chatter somewhat while the pll is reacquiring lock. the holdover function may retrigger, thereby preventing the holdover mode from ever terminating. use of the current source lock detect mode is recommended to avoid this situation (see the current source digital lock detect section). when in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. as in the external holdover mode, the b counter (in the n divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path pfd event. this helps to align the edges out of the r and n dividers for faster settling of the pll and reduce frequency errors during settling. because the prescaler is not reset, this feature works best when the b and r numbers are close because this results in a smaller phase difference for the loop to settle out. after leaving holdover, the loop then reacquires lock, and the ld pin must charge (if register 0x01d[3] = 1) before it can re-enter holdover (cp high impedance). the holdover function always responds to the state of the currently selected reference (register 0x01c). if the loop loses lock during a reference switchover (see the reference switchover section), holdover is triggered briefly until the next reference clock edge at the pfd. 07972-069 no no no no yes yes yes yes yes pll enabled dld == low was ld pin == high when dld went low? high impedance charge pump reference edge at pfd? release charge pump high impedance dld == high loop out of lock. digital lock detect signal goes low when the loop leaves lock as determined by the phase difference at the input of the pfd. analog lock detect pin indicates lock was previously achi eved. register 0x1d[3] = 1: use ld pin voltage with holdover. register 0x1d[3] = 0: ignore ld pin voltage,treat ld pin as always high. charge pump is made high impedance. pll counters continue operating normally. charge pump remains high impedance until the reference has returned. take charge pump out of high impedance. pll can now resettle. wait for dld to go high. this takes 5 to 255 cycles (programming of the dld delay counter) with the reference and feedback clocks inside the lock window at the pfd. this ensures that the holdover function waits for the pll to settle and lock before the holdover function can be retriggered. yes figure 41. flowchart of automatic/internal holdover mode
ad9516-5 rev. a | page 34 of 76 t he following registers affect the internal/automatic holdover function: ? register 0x018[3] = 0b; dld normal operation. ? register 0x01a[5:0] = 000100b; current source lock detect mode. ? register 0x018[6:5], lock detect counter. these bits change how many pfd cycles with edges inside the lock detect window are required for the dld indicator to indicate lock. this impacts the time required before the ld pin can begin to charge, as well as the delay from the end of a holdover event until the holdover function can be reengaged. ? register 0x01b[7:0] = 0xf7; set refmon pin to status of ref1 (active low). ? register 0x01c[2:1] = 11b; enable ref1 and ref2 input buffers. ? register 0x01d[3] = 1b; enable ld pin comparator. ? register 0x01d[2] = 1b; enable holdover function. ? register 0x018[3], disable digital lock detect. this bit must be set to 0b to enable the dld circuit. internal/automatic holdover does not operate correctly without the dld function enabled. ? register 0x01d[1] = 0b; use internal/automatic holdover mode. ? register 0x01d[0] = 1b; enable holdover function (complete vco calibration before enabling this bit). ? register 0x01a[5:0], lock detect pin output select. set this to 000100b to put it in the current source lock detect mode if using the ld pin comparator. load the ld pin with a capacitor of an appropriate value. ? register 0x232 = 0x01; update all registers. and, finally, ? connect refmon pin to refsel pin. ? register 0x01d[3], ld pin comparator enable. 1b = enable; 0b = disable. when disabled, the holdover function always senses the ld pin as high. frequency status monitors the ad9516 contains three frequency status monitors that are used to indicate if the pll reference (or references, in the case of single-ended mode) and the vco have fallen below a threshold frequency. figure 42 is a diagram that shows their location in the pll. ? register 0x01d[1], external holdover control. ? register 0x01d[0] and register 0x01d[2], holdover enable. if holdover is disabled, both external and automatic/internal holdover are disabled. f or example, to use automatic holdover with the following: the pll reference frequency monitors have two threshold frequencies: normal and extended (see table 12 ). the reference frequency monitor thresholds are selected in register 0x01b[7:5]. the reference frequency monitor status can be found in register 0x01f[3:1]. ? digital lock detect: five pfd cycles, high range window ? automatic holdover using the ld pin comparator s et the following registers (in addition to the normal pll registers): ? register 0x018[6:5] = 00b; lock detect counter = five cycles. ? register 0x018[4] = 0b; lock detect window = high range. programmable n delay refin (ref1) refin (ref2) clk clk ref1 ref2 status status r divider programmable r delay reference switchover ref_sel cprset v cp v s gnd rset distribution reference refmon cp status ld p, p + 1 prescaler a/b counters n divider phase frequency detector lock detect charge pump pll reference hold 01 0 1 divide by 2, 3, 4, 5, or 6 07972-070 clk frequency status figure 42. reference and clk status monitors
ad9516-5 rev. a | page 35 of 76 clock distribution a clock channel consists of a pair (or double pair, in the case of cmos) of outputs that share a common divider. a clock output consists of the drivers that connect to the output pins. the clock outputs have either lvpecl or lvds/cmos signal levels at the pins. the ad9516 has five clock channels: three channels are lvpecl (six outputs); two channels are lvds/cmos (up to four lvds outputs, or up to eight cmos outputs). each channel has its own programmable divider that divides the clock frequency that is applied to its input. the lvpecl channel dividers can divide by any integer from 2 to 32, or the divider can be bypassed to achieve a divide-by-1. each lvds/cmos channel divider contains two of these divider blocks in a cascaded configuration. the total division of the channel is the product of the divide value of the cascaded dividers. this allows divide values of (1 to 32) (1 to 32), or up to 1024 (note that this is not all values from 1 to 1024 but only the set of numbers that are the product of the two dividers). the vco divider can be set to divide by 2, 3, 4, 5, or 6 and must be used if the external clock signal connected to the clk input is greater than 1600 mhz. the channel dividers allow for a selection of various duty cycles, depending on the currently set division. that is, for any specific division, d, the output of the divider can be set to high for n + 1 input clock cycles and low for m + 1 input clock cycles (where d = n + m + 2). for example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can be high for three divider input cycles and low for two cycles. other combinations are also possible. the channel dividers include a duty-cycle correction function that can be disabled. in contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. however, this requires that the division be set by m = n + 1. in addition, the channel dividers allow a coarse phase offset or delay to be set. depending on the division selected, the output can be delayed by up to 31 input clock cycles. the divider outputs can also be set to start high or start low. operating modes there are two clock distribution operating modes. these operating modes are shown in table 25 . it is not necessary to use the vco divider if the clk frequency is less than the maximum channel divider input frequency (1600 mhz); otherwise, the vco divider must be used to reduce the frequency going to the channel dividers. table 25. clock distribution operating modes mode 0x1e1[0] vco divider 2 0 used 1 1 not used clk direct to lvpecl outputs it is possible to connect the clk directly to the lvpecl outputs, out0 to out5. however, the lvpecl outputs may not be able to provide full a voltage swing at the highest frequencies. to connect the lvpecl outputs directly to the clk input, the vco divider must be selected as the source to the distribution section even if no channel uses it. table 26. settings for routing vco divider input directly to lvpecl outputs register setting selection 0x1e1[0] = 0b vco divider selected 0x192[1] = 1b direct to out0, out1 outputs 0x195[1] = 1b direct to out2, out3 outputs 0x198[1] = 1b direct to out4, out5 outputs clock frequency division the total frequency division is a combination of the vco divider (when used) and the channel divider. when the vco divider is used, the total division from the vco or clk to the output is the product of the vco divider (2, 3, 4, 5, and 6) and the division of the channel divider. table 27 and table 28 indicate how the frequency division for a channel is set. for the lvpecl outputs, there is only one divider per channel. for the lvds/ cmos outputs, there are two dividers (x.1, x.2) cascaded per channel. table 27. frequency division for divider 0 to divider 2 vco divider setting channel divider setting clk direct to output setting frequency division 2 to 6 dont care enable 1 2 to 6 bypass disable (2 to 6) (1) 2 to 6 2 to 32 disable (2 to 6) (2 to 32) vco divider bypassed bypass no 1 vco divider bypassed 2 to 32 no 2 to 32 table 28. frequency division for divider 3 and divider 4 channel divider setting vco divider setting x.1 x.2 resulting frequency division 2 to 6 bypass bypass (2 to 6) (1) (1) 2 to 6 2 to 32 bypass (2 to 6) (2 to 32) (1) 2 to 6 2 to 32 2 to 32 (2 to 6) (2 to 32) (2 to 32) bypass 1 1 1 bypass 2 to 32 1 (2 to 32) (1) bypass 2 to 32 2 to 32 2 to 32 (2 to 32) the channel dividers feeding the lvpecl output drivers contain one 2-to-32 frequency divider. this divider provides for division by 2 to 32. division by 1 is accomplished by bypassing the divider. the dividers also provide for a programmable duty cycle, with optional duty-cycle correction when the divide ratio is odd.
ad9516-5 rev. a | page 36 of 76 a phase offset or delay in increments of the input clock cycle is selectable. the channel dividers operate with a signal at their inputs up to 1600 mhz. the features and settings of the dividers are selected by programming the appropriate setup and control registers (see table 47 through table 57 ). vco divider the vco divider provides frequency division between the external clk input and the clock distribution channel dividers. the vco divider can be set to divide by 2, 3, 4, 5, or 6 (see table 55 , register 0x1e0[2:0]). channel dividerslvpecl outputs each pair of lvpecl outputs is driven by a channel divider. there are three channel dividers (0, 1, and 2) driving six lvpecl outputs (out0 to out5). table 29 lists the register locations used for setting the division and other functions of these dividers. the division is set by the values of m and n. the divider can be bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. the duty-cycle correction can be enabled or disabled according to the setting of the dccoff bits. table 29. setting d x for divider 0, divider 1, and divider 2 1 divider low cycles m high cycles n bypass dccoff 0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0] 1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0] 2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0] 1 note that the value stored in the register = # of cycles minus 1. for example, 0x190[7:4] = 0001b equals two low cycl es (m = 2) for divider 0. channel frequency division (0, 1, and 2) for each channel (where the channel number is x: 0, 1, or 2), the frequency division, d x , is set by the values of m and n (four bits each, representing decimal 0 to decimal 15), where number of low cycles = m + 1 number of high cycles = n + 1 the cycles are cycles of the clock signal currently routed to the input of the channel dividers (vco divider out or clk). when a divider is bypassed, d x = 1. otherwise, d x = (n + 1) + (m + 1) = n + m + 2. this allows each channel divider to divide by any integer from 2 to 32. d uty cycle and duty-cycle correction (0, 1, and 2) t he duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: ? what are the m and n values for the channel? ? is the dcc enabled? ? is the vco divider used? ? what is the clk input duty cycle? t he dcc function is enabled, by default, for each channel divider. however, the dcc function can be disabled individually for each channel divider by setting the dccoff bit for that channel. c ertain m and n values for a channel divider result in a non-50% duty cycle. a non-50% duty cycle can also result with an even division, if m n. the duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. duty-cycle correction requires the following channel divider conditions: ? an even division must be set as m = n ? an odd division must be set as m = n + 1 when not bypassed or corrected by the dcc function, the duty cycle of each channel divider output is the numerical value of (n + 1)/(n + m + 2), expressed as a percentage (%). table 30 to tabl e 32 list the duty cycles at the output of the channel dividers for various configurations. table 30. duty cycle with vco divider, input duty cycle is 50% d x output duty cycle vco divider n + m + 2 dccoff = 1 dccoff = 0 even 1 (divider bypassed) 50% 50% odd = 3 1 (divider bypassed) 33.3% 50% odd = 5 1 (divider bypassed) 40% 50% even, odd even (n + 1)/ (n + m + 2) 50%, requires m = n even, odd odd (n + 1)/ (n + m + 2) 50%, requires m = n + 1 table 31. duty cycle with vco divider, input duty cycle is x% d x output duty cycle vco divider n + m + 2 dccoff = 1 dccoff = 0 even 1 (divider bypassed) 50% 50% odd = 3 1 (divider bypassed) 33.3% (1 + x%)/3 odd = 5 1 (divider bypassed) 40% (2 + x%)/5 even even (n + 1)/ (n + m + 2) 50%, requires m = n odd (n + 1)/ (n + m + 2) 50%, requires m = n + 1 odd = 3 even (n + 1)/ (n + m + 2) 50%, requires m = n odd = 3 odd (n + 1)/ (n + m + 2) (3n + 4 + x%)/(6n + 9), requires m = n + 1 odd = 5 even (n + 1)/ (n + m + 2) 50%, requires m = n odd = 5 odd (n + 1)/ (n + m + 2) (5n + 7 + x%)/(10n + 15), requires m = n + 1
ad9516-5 rev. a | page 37 of 76 table 32. channel divider output duty cycle when the vco divider is not used d x output duty cycle input clock duty cycle n + m + 2 dccoff = 1 dccoff = 0 any channel divider bypassed 1 (divider bypassed) same as input duty cycle any even (n + 1)/ (m + n + 2) 50%, requires m = n 50% odd (n + 1)/ (m + n + 2) 50%, requires m = n + 1 x% odd (n + 1)/ (m + n + 2) (n + 1 + x%)/(2 n + 3), requires m = n + 1 if the clk input is routed directly to the output, the duty cycle of the output is the same as the clk input. phase offset or coarse time delay (0, 1, and 2) each channel divider allows for a phase offset, or a coarse time delay, to be programmed by setting register bits (see table 33 ). these settings determine the number of cycles (successive rising edges) of the channel divider input frequency by which to offset, or delay, the rising edge of the output of the divider. this delay is with respect to a nondelayed output (that is, with a phase offset of zero). the amount of the delay is set by five bits loaded into the phase offset (po) register, plus the start high (sh) bit for each channel divider. when the start high bit is set, the delay is also affected by the number of low cycles (m) that are programmed for the divider. the sync function must be used to make phase offsets effective (see the synchronizing the outputssync function section). table 33. setting phase offset and division for divider 0, divider 1, and divider 2 1 divider start high (sh) phase offset (po) low cycles (m) high cycles (n) 0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0] 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0] 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0] 1 note that the value stored in the register = # of cycles minus 1. for example, register 0x190[7:4] = 0001b equals two lo w cycles (m = 2) for divider 0. let t = delay (in seconds). c = delay (in cycles of clock signal at input to d x ). t x = period of the clock signal at the input of the divider, d x (in seconds). = 16 sh[4] + 8 po[3] + 4 po[2] + 2 po[1] + 1 po[0] the channel divide-by is set as n = high cycles and m = low cycles. case 1 for 15: t = t x c = t /t x = case 2 for 16: t = ( ? 16 + m + 1) t x c = t /t x by giving each divider a different phase offset, output-to-output delays can be set in increments of the channel divider input clock cycle. figure 43 shows the results of setting such a coarse offset between outputs. c h a n n e l d i v i d e r o u t p u t s d i v = 4 , d u t y = 5 0 % 0123456789101112131415 tx divider 0 divider 1 divider 2 channel divider input sh = 0 po = 0 sh = 0 po = 1 sh = 0 po = 2 1 tx 2 tx 07972-071 figure 43. effect of coarse phase offset (or delay) channel dividerslvds/cmos outputs channel divider 3 and channel divider 4 each drive a pair of lvds outputs, giving four lvds outputs (out6 to out9). alternatively, each of these lvds differential outputs can be configured individually as a pair (a and b) of cmos single- ended outputs, providing for up to eight cmos outputs. by default, the b output of each pair is off but can be turned on as desired. channel divider 3 and channel divider 4 each consist of two cascaded, 2 to 32, frequency dividers. the channel frequency division is d x.1 d x.2 , or up to 1024. divide-by-1 is achieved by bypassing one or both of these dividers. both of the dividers also have dcc enabled by default, but this function can be disabled, if desired, by setting the dccoff bit of the channel. a coarse phase offset or delay is also programmable (see the phase offset or coarse time delay (divider 3 and divider 4) section). the channel dividers operate up to 1600 mhz. the features and settings of the dividers are selected by programming the appropriate setup and control registers (see table 47 and table 48 through table 5 7 ). table 34. setting division (d x ) for divider 3 and divider 4 1 divider m n bypass dccoff 3 3.1 0x199[7:4] 0x199[3:0] 0x19c[4] 0x19d[0] 3.2 0x19b[7:4] 0x19b[3 :0] 0x19c[5] 0x19d[0] 4 4.1 0x19e[7:4] 0x19e[3:0] 0x1a1[4] 0x1a2[0] 4.2 0x1a0[7:4] 0x1a0[3:0] 0x1a1[5] 0x1a2[0] 1 note that the value stored in the register = # of cycles minus 1. for example, register 0x199[7:4] = 0001b equals two lo w cycles (m = 2) for divider 3.1.
ad9516-5 rev. a | page 38 of 76 channel frequency division (divider 3 and divider 4) the division for each channel divider is set by the bits in the registers for the individual dividers (x.y = 3.1, 3.2, 4.1, and 4.2). number of low cycles = m x.y + 1 number of high cycles = n x.y + 1 when both x.1 and x.2 are bypassed, d x = 1 1 = 1. when only x.2 is bypassed, d x = (n x.1 + m x.1 + 2) 1. when both x.1 and x.2 are not bypassed, d x = (n x.1 + m x.1 + 2) (n x.2 + m x.2 + 2). by cascading the dividers, channel division up to 1024 can be obtained. however, not all integer value divisions from 1 to 1024 are obtainable; only the values that are the product of the separate divisions of the two dividers (d x.1 d x.2 ) can be realized. if only one divider is needed when using divider 3 and divider 4, use the first one (x.1) and bypass the second one (x.2). do not bypass x.1 and use x.2. duty cycle and duty-cycle correction (divider 3 and divider 4) t he same duty cycle and dcc considerations apply to divider 3 and divider 4 as to divider 0, divider 1, and divider 2 (see the duty cycle and duty-cycle correction (0, 1, and 2) section); however, with these channel dividers, the number of possible configurations is more complex. d uty-cycle correction on divider 3 and divider 4 requires the following channel divider conditions: ? an even d x.y must be set as m x.y = n x.y (low cycles = high cycles). ? an odd d x.y must be set as m x.y = n x.y + 1 (number of low cycles must be one greater than the number of high cycles). ? if only one divider is bypassed, it must be the second divider, x.2. ? if only one divider has an even divide-by, it must be the second divider, x.2. the possibilities for the duty cycle of the output clock from divider 3 and divider 4 are shown in table 35 through table 39 . table 35. divider 3 and divide r 4 duty cycle; vco divider used; duty cycle correction off (dccoff = 1) d x.1 d x.2 vco divider n x.1 + m x.1 + 2 n x.2 + m x.2 + 2 output duty cycle even bypassed bypassed 50% odd = 3 bypassed bypassed 33.3% odd = 5 bypassed bypassed 40% even even, odd bypassed (n x.1 + 1)/ (n x.1 + m x.1 + 2) odd even, odd bypassed (n x.1 + 1)/ (n x.1 + m x.1 + 2) even even, odd even, odd (n x.2 + 1)/ (n x.2 + m x.2 + 2) odd even, odd even, odd (n x.2 + 1)/ (n x.2 + m x.2 + 2) table 36. divider 3 and divide r 4 duty cycle; vco divider not used; duty cycle correction off (dccoff = 1) d x.1 d x.2 input clock duty cycle n x.1 + m x.1 + 2 n x.2 + m x.2 + 2 output duty cycle 50% bypassed bypassed 50% x% bypassed bypassed x% 50% even, odd bypassed (n x.1 + 1)/ (n x.1 + m x.1 + 2) x% even, odd bypassed (n x.1 + 1)/ (n x.1 + m x.1 + 2) 50% even, odd even, odd (n x.2 + 1)/ (n x.2 + m x.2 + 2) x% even, odd even, odd (n x.2 + 1)/ (n x.2 + m x.2 + 2) table 37. divider 3 and divide r 4 duty cycle; vco divider used; duty cycle correction on (dccoff = 0); vco divider input duty cycle = 50% d x.1 d x.2 vco divider n x.1 + m x.1 + 2 n x.2 + m x.2 + 2 output duty cycle even bypassed bypassed 50% odd bypassed bypassed 50% even even (n x.1 = m x.1 ) bypassed 50% odd even (n x.1 = m x.1 ) bypassed 50% even odd (m x.1 = n x.1 + 1) bypassed 50% odd odd (m x.1 = n x.1 + 1) bypassed 50% even even (n x.1 = m x.1 ) even (n x.2 = m x.2 ) 50% odd even (n x.1 = m x.1 ) even (n x.2 = m x.2 ) 50% even odd (m x.1 = n x.1 + 1) even (n x.2 = m x.2 ) 50% odd odd (m x.1 = n x.1 + 1) even (n x.2 = m x.2 ) 50% even odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) 50% odd odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) 50%
ad9516-5 rev. a | page 39 of 76 table 38. divider 3 and divide r 4 duty cycle; vco divider used; duty cycle correction on (dccoff = 0); vco divider input duty cycle = x% d x.1 d x.2 vco divider n x.1 + m x.1 + 2 n x.2 + m x.2 + 2 output duty cycle even bypassed bypassed 50% odd = 3 bypassed bypassed (1 + x%)/3 odd = 5 bypassed bypassed (2 + x%)/5 even even (n x.1 = m x.1 ) bypassed 50% odd even (n x.1 = m x.1 ) bypassed 50% even odd (m x.1 = n x.1 + 1) bypassed 50% odd = 3 odd (m x.1 = n x.1 + 1) bypassed (3n x.1 + 4 + x%)/ (6n x.1 + 9) odd = 5 odd (m x.1 = n x.1 + 1) bypassed (5n x.1 + 7 + x%)/ (10n x.1 + 15) even even (n x.1 = m x.1 ) even (n x.2 = m x.2 ) 50% odd even (n x.1 = m x.1 ) even (n x.2 = m x.2 ) 50% even odd (m x.1 = n x.1 + 1) even (n x.2 = m x.2 ) 50% odd odd (m x.1 = n x.1 + 1) even (n x.2 = m x.2 ) 50% even odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) 50% odd = 3 odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) (6n x.1 n x.2 + 9n x.1 + 9n x.2 + 13 + x%)/ (3(2n x.1 + 3) (2n x.2 + 3)) odd = 5 odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) (10n x.1 n x.2 + 15n x.1 + 15n x.2 + 22 + x%)/ (5(2 n x.1 + 3) (2 n x.2 + 3)) table 39. divider 3 and divide r 4 duty cycle; vco divider not used; duty cycle correction on (dccoff = 0) d x.1 d x.2 input clock duty cycle n x.1 + m x.1 + 2 n x.2 + m x.2 + 2 output duty cycle 50% bypassed bypassed 50% 50% even (n x.1 = m x.1 ) bypassed 50% x% bypassed bypassed x% (high) x% even (n x.1 = m x.1 ) bypassed 50% 50% odd (m x.1 = n x.1 + 1) bypassed 50% odd (m x.1 = n x.1 + 1) bypassed (n x.1 + 1 + x%)/ (2n x.1 + 3) x% odd (m x.1 = n x.1 + 1) bypassed (n x.1 + 1 + x%)/ (2n x.1 + 3) 50% even (n x.1 = m x.1 ) even (n x.2 = m x.2 ) 50% x% even (n x.1 = m x.1 ) even (n x.2 = m x.2 ) 50% 50% odd (m x.1 = n x.1 + 1) even (n x.2 = m x.2 ) 50% x% odd (m x.1 = n x.1 + 1) even (n x.2 = m x.2 ) 50% 50% odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) 50% x% odd (m x.1 = n x.1 + 1) odd (m x.2 = n x.2 + 1) (2n x.1 n x.2 + 3n x.1 + 3n x.2 + 4 + x%)/ ((2n x.1 + 3)(2n x.2 + 3)) phase offset or coarse time delay (divider 3 and divider 4) divider 3 and divider 4 can be set to have a phase offset or delay. the phase offset is set by a combination of the bits in the phase offset and start high registers (see table 4 0 ). table 40. setting phase offset and division for divider 3 and divider 4 1 divider start high (sh) phase offset (po) low cycles m high cycles n 3 3.1 0x19c[0] 0x19a[3:0] 0x199[7:4] 0x199[3:0] 3.2 0x19c[1] 0x19a[7:4] 0x19b[7:4] 0x19b[3:0] 4 4.1 0x1a1[0] 0x19f[3:0] 0x19e[7:4] 0x19e[3:0] 4.2 0x1a1[1] 0x19f[7:4] 0x1a0[7:4] 0x1a0[3:0] 1 note that the value stored in the register is equal to the number of cycles minus 1. for example, register 0x199[ 7:4] = 0001b equals two low cycles (m = 2) for divider 3.1.
ad9516-5 rev. a | page 40 of 76 let t = delay (in seconds). x.y = 16 sh[0] + 8 po[3] + 4 po[2] + 2 po[1] + 1 po[0]. t x.1 = period of the clock signal at the input to d x.1 (in seconds). t x.2 = period of the clock signal at the input to d x.2 (in seconds). case 1 when x.1 15 and x.2 15: t = x.1 t x.1 + x.2 t x.2 case 2 when x.1 15 and x.2 16: t = x.1 t x.1 + ( x.2 C 16 + m x.2 + 1) t x.2 case 3 when x.1 16 and x.2 15: t = ( x.1 ? 16 + m x.1 + 1) t x.1 + x.2 t x.2 case 4 when x.1 16 and x.2 16: t = ( x.1 ? 16 + m x.1 + 1) t x.1 + ( x.2 ? 16 + m x.2 + 1) t x.2 fine delay adjust (divider 3 and divider 4) each ad9516 lvds/cmos output (out6 to out9) includes an analog delay element that can be programmed to give variable time delays ( t ) in the clock signal at that output. divider x.2 divider x.1 ? t outm outm bypass fine delay adjust cmos lvds cmos ? t outn outn bypass fine delay adjust cmos lvds cmos output drivers clk vco divider 07972-072 figure 44. fine delay (out6 to out9) the amount of delay applied to the clock signal is determined by programming four registers per output (see table 41). table 41. setting analog fine delays output (lvds/cmos) ramp capacitors ramp current delay fraction delay bypass out6 0x0a1[5:3] 0x0a1[2: 0] 0x0a2[5:0] 0x0a0[0] out7 0x0a4[5:3] 0x0a4[2: 0] 0x0a5[5:0] 0x0a3[0] out8 0x0a7[5:3] 0x0a7[2: 0] 0x0a8[5:0] 0x0a6[0] out9 0x0aa[5:3] 0x0aa[2: 0] 0x0ab[5:0] 0x0a9[0] calculating the fine delay the following values and equations are used to calculate the delay of the delay block. i ramp (a) = 200 ( ramp current + 1) number of capacitors = number of bits = 0 in ramp capacitor s + 1 example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1. delay range (ns) = 200 (( no. of caps + 3)/( i ramp )) 1.3286 ?? ?? 6 1 10 16000.34ns 4 ? ? ? ? ? ? ? ? ? ? ????? ? ramp ramp i capsofno. i offset delay full scale (ns) = delay range + offset fine delay (ns) = delay range delay fraction (1/63) + offset note that only delay fraction values up to 47 decimal (101111b; 0x02f) are supported. in no case can the fine delay exceed one-half of the output clock period. if a delay longer than half of the clock period is attempted, the output stops clocking. the delay function adds some jitter that is greater than that specified for the nondelayed output. this means that the delay function should be used primarily for clocking digital chips, such as fpga, asic, duc, and ddc. an output with this delay enabled may not be suitable for clocking data converters. the jitter is higher for long full scales because the delay block uses a ramp and trip points to create the variable delay. a slower ramp time produces more time jitter. synchronizing the outputssync function the ad9516 clock outputs can be synchronized to each other. outputs can be individually excluded from synchronization. synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and, subsequently, releasing these outputs to continue clocking at the same instant with the preset conditions applied. this allows for the alignment of the edges of two or more outputs or for the spacing of edges according to the coarse phase offset settings for two or more outputs. synchronization of the outputs is executed in several ways: ? by forcing the sync pin and then releasing it (manual sync) ? by setting and then resetting any one of the following three bits: the soft sync bit (register 0x230[0]), the soft reset bit (register 0x000[2] [mirrored]), or the power-down distribution reference bit (register 0x230[1]) ? by executing synchronization of the outputs as part of the chip power-up sequence ? by forcing the reset pin low, then releasing it (chip reset) ? by forcing the pd pin low, then releasing it (chip power-down)
ad9516-5 rev. a | page 41 of 76 the most common way to execute the sync function is to use the sync pin to do a manual synchronization of the outputs. this requires a low going signal on the sync pin, which is held low and then released when synchronization is desired. the timing of the sync operation is shown in (using vco divider) and (vco divider not used). there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the sync signal with respect to the clock edges inside the . the delay from the figure 45 figure 46 ad9516 sync rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the vco divider input (see ), or one cycle of the clk input (see ), depending on whether the vco divider is used. cycles are counted from the rising edge of the signal. figure 45 figure 46 another common way to execute the sync function is by setting and resetting the soft sync bit at register 0x230[0] (see table 47 through table 5 7 for details). both the setting and resetting of the soft sync bit require an update all registers operation (register 0x232[0] = 1) to take effect. 1234567 8 910 input to vco divider input to channel divider output of channel divider s ync pin 1 11 12 13 14 14 to 15 cycles at channel divider input + 1 cycle at vco divider input channel divider output static channel divide r output clocking channel divide r output clocking 07972-073 figure 45. sync timing when vco divider is usedclk or vco is input input to clk input to channel divide r output of channel divider sync pin 14 to 15 cycles at channel divider input + 1 cycle at clk input 1234567 8 910 11 12 13 14 1 channel divider output static channel divide r output clocking channel divide r output clocking 0 7972-074 figure 46. sync timing when vco di vider is not usedclk input only
ad9516-5 rev. a | page 42 of 76 a sync operation brings all outputs that have not been excluded (by the nosync bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. the preset condition takes into account the settings in each of the channels start high bit and its phase offset. these settings govern both the static state of each output when the sync operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the sync operation. between outputs and after synchronization, this allows for the setting of phase offsets. the ad9516 outputs are in pairs, sharing a channel divider per pair (two pairs of pairs, four outputs, in the case of cmos). the synchronization conditions apply to both outputs of a pair. each channel (a divider and its outputs) can be excluded from any sync operation by setting the nosync bit of the channel. channels that are set to ignore sync (excluded channels) do not set their outputs static during a sync operation, and their outputs are not synchronized with those of the nonexcluded channels. clock outputs the ad9516 offers three output level choices: lvpecl, lvds, and cmos. out0 to out5 are lvpecl differential outputs; and out6 to out9 are lvds/cmos outputs. these outputs can be configured as either lvds differential or as pairs of single-ended cmos outputs. lvpecl outputsout0 to out5 the lvpecl differential voltage (vod) is selectable from 400 mv to 960 mv (see register 0x0f0[3:2] to register 0x0f5[3:2]). the lvpecl outputs have dedicated pins for power supply (vs_lvpecl), allowing a separate power supply to be used. v s_lvpecl can range from 2.5 v to 3.3 v. gnd 3.3v out out 07972-033 figure 47. lvpecl output, si mplified equivalent circuit the lvpecl output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. each lvpecl output can be powered down or powered up as needed. because of the architecture of the lvpecl output stages, there is the possibility of electrical overstress and breakdown under certain power-down conditions. for this reason, the lvpecl outputs have several power-down modes. this includes a safe power-down mode that continues to protect the output devices while powered down, although it consumes somewhat more power than a total power-down. if the lvpecl output pins are terminated, it is best to select the safe power-down mode. if the pins are not connected (unused), it is acceptable to use the total power-down mode. lvds/cmos outputsout6 to out9 out6 to out9 can be configured as either an lvds differential output or as a pair of cmos single-ended outputs. the lvds outputs allow for selectable output current from ~1.75 ma to ~7 ma. out out 3 .5m a 3 .5m a 07972-034 figure 48. lvds output, simplified equivalent circuit with 3.5 ma typical current source the lvds output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change. each lvds output can be powered down, if not needed, to save power. out6 to out9 can also be cmos outputs. each lvds output can be configured to be two cmos outputs. this provides for up to eight cmos outputs: out6a, out6b, out7a, out7b, out8a, out8b, out9a, and out9b. when an output is configured as cmos, the cmos output a is automatically turned on. the cmos output b can be turned on or off independently. the relative polarity of the cmos outputs can also be selected for any combination of inverting and noninverting. see table 52 : register 0x140[7:5], register 0x141[7:5], register 0x142[7:5], and register 0x143[7:5]. each lvds/cmos output can be powered down, as needed, to save power. the cmos output power-down is controlled by the same bit that controls the lvds power-down for that output. this power-down control affects both cmos output a and cmos output b. however, when cmos output a is powered up, cmos output b output can be powered on or off separately. out1/ out1 v s 07972-035 figure 49. cmos equiva lent output circuit
ad9516-5 rev. a | page 43 of 76 reset modes the ad9516 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active. power-on resetstart-up conditions when vs is applied a power-on reset (por) is issued when the vs power supply is turned on. the por pulse duration is <100 ms and initializes the chip to the power-on conditions that are determined by the default register settings. these are indicated in the default value (hex) column of table 47 . at power-on, the ad9516 also executes a sync operation, which brings the outputs into phase alignment according to the default settings. it is recommended that the user not toggle sclk during the reset pulse. asynchronous reset via the reset pin an asynchronous hard reset is executed by momentarily pulling reset low. a reset restores the chip registers to the default settings. it is recommended that the user not toggle sclk for 20 ns after reset goes high. soft reset via register 0x000[2] a soft reset is executed by writing register 0x000[2] and register 0x000[5] = 1b. this bit is not self-clearing; therefore, it must be cleared by writing register 0x000[2] and register 0x000[2] = 0b to reset it and complete the soft reset operation. a soft reset restores the default values to the internal registers. the soft reset bit does not require an update registers command (register 0x232 = 0x01) to be issued. power-down modes chip power-down via pd the ad9516 can be put into a power-down condition by pulling the pd pin low. power-down turns off most of the functions and currents inside the . the chip remains in this power-down state until ad9516 pd is brought back to logic high. when the wakes up, it returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the ad9516 pd pin is held low. t he pd power-down shuts down the currents on the chip, except the bias current that is necessary to maintain the lvpecl outputs in a safe shutdown mode. this is needed to protect the lvpecl output circuitry from damage that can be caused by certain termination and load configurations when tristated. because this is not a complete power-down, it can be called sleep mode. w hen the ad9516 is in a pd power-down, the chip is in the following state: ? the pll is off (asynchronous power-down). ? the clk input buffer is off. ? all dividers are off. ? all lvds/cmos outputs are off. ? all lvpecl outputs are in safe off mode. ? the serial port is active and responds to commands. if the ad9516 clock outputs must be synchronized to each other, a sync is required upon exiting power-down (see the synchronizing the outputssync function section). pll power-down the pll section of the ad9516 can be selectively powered down. there are three pll operating modes that are set by register 0x010[1:0], as shown in table 49 . in asynchronous power-down mode, the device powers down as soon as the registers are updated. in synchronous power-down mode, the pll power-down is gated by the charge pump to prevent unwanted frequency jumps. the device goes into power-down on the occurrence of the next charge pump event after the registers are updated. distribution power-down the distribution section can be powered down by writing to register 0x230[1] = 1b. this turns off the bias to the distribution section. if the lvpecl power-down mode is normal operation (00b), it is possible for a low impedance load on that lvpecl output to draw significant current during this power-down. if the lvpecl power-down mode is set to 11b, the lvpecl output is not protected from reverse bias and can be damaged under certain termination conditions. individual clock output power-down any of the clock distribution outputs can be powered down individually by writing to the appropriate registers. the register map details the individual power-down settings for each output. the lvds/cmos outputs can be powered down, regardless of their output load configuration. the lvpecl outputs have multiple power-down modes (see table 53 ) that give some flexibility in dealing with the various output termination conditions. when the mode is set to 10b, the lvpecl output is protected from reverse bias to 2 vbe + 1 v. if the mode is set to 11b, the lvpecl output is not protected from reverse bias and can be damaged under certain termination conditions. this setting also affects the operation when the distribution block is powered down with 0x230[1] = 1b (see the distribution power-down section). individual circuit block power-down other ad9516 circuit blocks (such as clk, ref1, and ref2) can be powered down individually. this gives flexibility in configuring the part for power savings whenever certain chip functions are not needed.
ad9516-5 rev. a | page 44 of 76 serial control port the ad9516 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. the ad9516 serial control port is compatible with most synchronous transfer formats, including both the motorola spi? and intel? ssr? protocols. the serial control port allows read/write access to all registers that configure the ad9516 . single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9516 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unidirectional i/o pins (sdio/sdo). by default, the ad9516 is in bidirectional mode, long instruction (long instruction is the only instruction mode supported). serial control port pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled down by a 30 k resistor to ground. sdio (serial data input/output) is a dual-purpose pin that acts as either an input only (unidirectional mode) or as both an input/ output (bidirectional mode). the ad9516 defaults to the bidirectional i/o mode (register 0x000[0] = 0b). sdo (serial data output) is used only in the unidirectional i/o mode (register 0x000[0] = 1b) as a separate output pin for reading back data. cs (chip select bar) is an active low control that gates the read and write cycles. when cs is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 30 k resistor to vs. ad9516-5 serial control port sclk 16 cs 17 sdo 21 sdio 22 07972-036 figure 50. serial control port general operation of serial control port a write or a read operation to the ad9516 is initiated by pulling cs low. cs stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see ). in these modes, table 42 cs can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. cs can go high on byte boundaries only and during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset, either by completing the remaining transfers or by returning the cs low for at least one complete sclk cycle (but less than eight sclk cycles). raising the cs on a nonbyte boundary terminates the serial transfer and flushes the buffer. in streaming mode (see table 42 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). cs must be raised at the end of the last byte to be transferred, thereby ending the stream mode. communication cycleinstruction plus data there are two parts to a communication cycle with the ad9516. the first part writes a 16-bit instruction word into the ad9516, coincident with the first 16 sclk rising edges. the instruction word provides the ad9516 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the ad9516 . data bits are registered on the rising edge of sclk. the length of the transfer (1, 2, or 3 bytes or streaming mode) is indicated by two bits ([w1:w0]) in the instruction byte. when the transfer is 1, 2, or 3 bytes, but not streaming, cs can be raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). when the bus is stalled, the serial transfer resumes when cs is lowered. raising cs on a nonbyte boundary resets the serial control port. during a write, streaming mode does not skip over reserved or unused registers; therefore, the user must know the correct bit pattern to write to the reserved registers to preserve proper operation of the part. refer to the register map (see ) to determine if the default value for reserved registers is nonzero. it does not matter what data is written to blank or unused registers. table 47 because data is written into a serial control port buffer area, and not directly into the actual control registers of the ad9516 , an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the ad9516, thereby causing them to become active. the update registers operation consists of setting register 0x232[0] = 1b (this bit is self- clearing). any number of bytes of data can be changed before executing an update registers. the update registers operation simultaneously actuates all register changes that have been written to the buffer since any previous update.
ad9516-5 rev. a | page 45 of 76 read if the instruction word is for a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1 to 3, as determined by [w1:w0]. if n = 4, the read operation is in streaming mode, continuing until cs is raised. streaming mode does not skip over reserved or blank registers. the readback data is valid on the falling edge of sclk. the default mode of the ad9516 serial control port is the bidirectional mode. in bidirectional mode, both the sent data and the readback data appear on the sdio pin. it is also possible to set the ad9516 to unidirectional mode via the sdo active bit (register 0x000[0] = 1b). in unid irectional mode, the readback data appears on the sdo pin. a readback request reads the data that is in the serial control port buffer area, or the data that is in the active registers (see figure 51 ). readback of the buffer or active registers is controlled by register 0x004[0]. the ad9516 supports only the long instruction mode; therefore, register 0x000[4:3] must be set to 11b. (this register uses mirrored bits). long instruction mode is the default at power- up or reset. the ad9516 uses register address 0x000 to register address 0x232. sclk sdio sdo cs serial control port buffer registers update registers write register 0x232 = 0x01 to udate registers active registers 07972-037 figure 51. relationship between seri al control port buffer registers and active registers of the ad9516 instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits, [w1:w0], indicate the length of the transfer in bytes. the final 13 bits are the address ([a12:a0]) at which to begin the read or write operation. for a write, the instruction word is followed by the number of bytes of data indicated by bits[w1:w0], see table 42 . table 42. byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode the 13 bits found in bits[a12:a0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. only bits[a9:a0] are needed to cover the range of the 0x232 registers used by the ad9516 . bits[a12:a10] must always be set to 0b. for multibyte transfers, this address is the starting byte address. in msb first mode, subsequent bytes decrement the address. msb/lsb first transfers the ad9516 instruction word and byte data can be msb first or lsb first. any data written to register 0x000 must be mirrored; the upper four bits (bits[7:4]) must mirror the lower four bits (bits[3:0]). this makes it irrelevant whether lsb first or msb first is in effect. as an example of this mirroring, see the default setting for this register: 0x000, which mirrors bit 4 and bit 3. this sets the long instruction mode (which is the default and the only mode that is supported). the default for the ad9516 is msb first. when lsb first is set by register 0x000[1] and register 0x000[6], it takes effect immediately, because it affects only the operation of the serial control port and does not require that an update be executed. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes must follow, in order, from high address to low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle. when lsb first is active, the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the internal byte address generator of the serial control port increments for each byte of the multibyte transfer cycle. the ad9516 serial control port register address decrements from the register address just written toward 0x000 for multibyte i/o operations if the msb first mode is active (default). if the lsb first mode is active, the register address of the serial control port increments from the address just written toward register 0x232 for multibyte i/o operations. streaming mode always terminates when it hits address 0x232. note that unused addresses are not skipped during multibyte i/o operations. table 43. streaming mode (no addresses are skipped) write mode address direction stop sequence lsb first increment 0x230, 0x231, 0x232, stop msb first decrement 0x001, 0x000, 0x232, stop
ad9516-5 rev. a | page 46 of 76 table 44. serial control port, 16-bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 = 0 a11 = 0 a10 = 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 0 7972-038 figure 52. serial control port writemsb firs t, 16-bit instruction, two bytes of data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 07972-039 figure 53. serial control port readmsb firs t, 16-bit instruction, four bytes of data t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t high t low t sclk t c cs sclk sdio 0 7972-040 figure 54. serial control port writemsb firs t, 16-bit instruction, timing measurements data bit n ? 1 data bit n cs sclk sdio sdo t dv 07972-041 figure 55. timing diagram for serial control port register read cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 0 7972-042 figure 56. serial control port writelsb firs t, 16-bit instruction, two bytes of data
ad9516-5 rev. a | page 47 of 76 cs sclk sdio t high t low t sclk t s t ds t dh t c bit n bit n + 1 07972-043 figure 57. serial control port timingwrite table 45. serial control port timing parameter description t ds setup time between data and the rising edge of sclk t dh hold time between data and the rising edge of sclk t clk period of the clock setup time between the cs falling edge and the sclk rising ed ge (start of communication cycle) t s setup time between the sclk rising edge and the cs rising edge (end of communication cycle) t c t high minimum period that sclk should be in a logic high state t low minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 55 )
ad9516-5 rev. a | page 48 of 76 thermal performance table 46. thermal parameters for 64-lead lfcsp symbol thermal characteristic using a jedec jesd51-7 plus jedec jesd51-5 2s2p test board value (c/w) ja junction-to-ambient thermal resistance, natural convection per jedec jesd51-2 (still air) 22.0 jma junction-to-ambient thermal resistance, 1.0 m/sec airflow per jedec jesd51-6 (moving air) 19.2 jma junction-to-ambient thermal resistance, 2.0 m/sec airflow per jedec jesd51-6 (moving air) 17.2 jb junction-to-board characterization parameter, 1. 0 m/sec airflow per jedec jesd51-6 (moving air) and jedec jesd51-8 11.6 jc junction-to-case thermal resistance (die-to -heat sink) per mil-std 883, method 1012.1 1.3 jt junction-to-top-of-package characterization parameter, natural convection per jedec jesd51-2 (still air) 0.1 the ad9516 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine the junction temperature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the user at the top center of the package. jt is the value from table 46 . pd is the power dissipation of the device (see table 13. ) va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approximation of t j by the following equation: t j = t a + ( ja pd ) where t a is the ambient temperature (c). va lu e s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. va lu e s of jb are provided for package comparison and pcb design considerations.
ad9516-5 rev. a | page 49 of 76 register maps register map overview register addresses that are not listed in table 47 (as well as ones marked unused) are not used and writing to those registers has no effect. the user should write the default value only to the register addresses marked reserved. table 47. register map overview ref. addr. (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) serial port configuration 0x000 serial port configuration sdo active lsb first soft reset long instruction long instruction soft reset lsb first sdo active 0x18 0x001 blank 0x002 reserved 0x003 part id part id (read only) 0x01 0x004 readback control blank read back active registers 0x00 pll 0x010 pfd and charge pump pfd polarity charge pump current charge pu mp mode pll power-down 0x7d 0x011 r counter 14-bit r divi der, bits[7:0] (lsb) 0x01 0x012 blank 14-bit r divide r, bits[13:8] (msb) 0x00 0x013 a counter blank 6-bit a counter 0x00 0x014 b counter 13-bit b coun ter, bits[7:0] (lsb) 0x03 0x015 blank 13-bit b counter, bits[12:8] (msb) 0x00 0x016 pll control 1 set cp pin to v cp /2 reset r counter reset a and b counters reset all counters b counter bypass prescaler p 0x06 0x017 pll control 2 status pin control antibacklash pulse width 0x00 0x018 pll control 3 reserved lock detect counter digital lock detect window disable digital lock detect reserved 0x06 0x019 pll control 4 r, a, b counters sync pin reset r path delay n path delay 0x00 0x01a pll control 5 reserved reference frequency monitor threshold ld pin control 0x00 0x01b pll control 6 clk frequency monitor ref2 ( refin ) frequency monitor ref1 (refin) frequency monitor refmon pin control 0x00 0x01c pll control 7 disable switchover deglitch select ref2 use ref_sel pin reserved ref2 power-on ref1 power-on differential reference 0x00 0x01d pll control 8 reserved pll status register disable ld pin comparator enable holdover enable external holdover control holdover enable 0x00 0x01e pll control 9 reserved 0x00 0x01f pll readback (read-only) reserved holdover active ref2 selected clk frequency > threshold ref2 frequency > threshold ref1 frequency > threshold digital lock detect n/a 0x020 to 0x04f blank
ad9516-5 rev. a | page 50 of 76 ref. addr. (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) fine delay adjustout6 to out9 0x0a0 out6 delay bypass blank out6 delay bypass 0x01 0x0a1 out6 delay full-scale blank out6 ramp capacitors out6 ramp current 0x00 0x0a2 out6 delay fraction blank out6 delay fraction 0x00 0x0a3 out7 delay bypass blank out7 delay bypass 0x01 0x0a4 out7 delay full-scale blank out7 ramp capacitors out7 ramp current 0x00 0x0a5 out7 delay fraction blank out7 delay fraction 0x00 0x0a6 out8 delay bypass blank out8 delay bypass 0x01 0x0a7 out8 delay full-scale blank out8 ramp capacitors out8 ramp current 0x00 0x0a8 out8 delay fraction blank out8 delay fraction 0x00 0x0a9 out9 delay bypass blank out9 delay bypass 0x01 0x0aa out9 delay full-scale blank out9 ramp capacitors out9 ramp current 0x00 0x0ab out9 delay fraction blank out9 delay fraction 0x00 0x0ac to 0x0ef blank lvpecl outputs 0x0f0 out0 blank out0 invert out0 lvpecl differential voltage out0 power-down 0x08 0x0f1 out1 blank out1 invert out1 lvpecl differential voltage out1 power-down 0x0a 0x0f2 out2 blank out2 invert out2 lvpecl differential voltage out2 power-down 0x08 0x0f3 out3 blank out3 invert out3 lvpecl differential voltage out3 power-down 0x0a 0x0f4 out4 blank out4 invert out4 lvpecl differential voltage out4 power-down 0x08 0x0f5 out5 blank out5 invert out5 lvpecl differential voltage out5 power-down 0x0a 0x0f6 to 0x13f blank lvds/cmos outputs 0x140 out6 out6 cmos output polarity out6 cmos b out6 select lvds/cmos out6 lvds output current out6 power-down 0x42 0x141 out7 out7 cmos output polarity out7 cmos b out7 select lvds/cmos out7 lvds output current out7 power-down 0x43 0x142 out8 out8 cmos output polarity out8 cmos b out8 select lvds/cmos out8 lvds output current out8 power-down 0x42 0x143 out9 out9 cmos output polarity out9 cmos b out9 select lvds/cmos out9 lvds output current out9 power-down 0x43 0x144 to 0x18f blank
ad9516-5 rev. a | page 51 of 76 ref. addr. (hex) parameter bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) lvpecl channel dividers 0x190 divider 0 (pecl) divider 0 low cycles divi der 0 high cycles 0x00 0x191 divider 0 bypass divider 0 nosync divider 0 force high divider 0 start high divider 0 phase offset 0x80 0x192 blank divider 0 direct to output divider 0 dccoff 0x00 0x193 divider 1 (pecl) divider 1 low cycles divi der 1 high cycles 0xbb 0x194 divider 1 bypass divider 1 nosync divider 1 force high divider 1 start high divider 1 phase offset 0x00 0x195 blank divider 1 direct to output divider 1 dccoff 0x00 0x196 divider 2 (pecl) divider 2 low cycles divi der 2 high cycles 0x00 0x197 divider 2 bypass divider 2 nosync divider 2 force high divider 2 start high divider 2 phase offset 0x00 0x198 blank divider 2 direct to output divider 2 dccoff 0x00 lvds/cmos channel dividers 0x199 divider 3 (lvds/cmos) low cycles divider 3.1 high cycles divider 3.1 0x22 0x19a phase offset divider 3.2 phase offset divider 3.1 0x00 0x19b low cycles divider 3.2 high cycles divider 3.2 0x11 0x19c reserved bypass divider 3.2 bypass divider 3.1 divider 3 nosync divider 3 force high start high divider 3.2 start high divider 3.1 0x00 0x19d blank divider 3 dccoff 0x00 0x19e divider 4 (lvds/cmos) low cycles divider 4.1 high cycles divider 4.1 0x22 0x19f phase offset divider 4.2 phase offset divider 4.1 0x00 0x1a0 low cycles divider 4.2 high cycles divider 4.2 0x11 0x1a1 reserved bypass divider 4.2 bypass divider 4.1 divider 4 nosync divider 4 force high start high divider 4.2 start high divider 4.1 0x00 0x1a2 blank divider 4 dccoff 0x00 0x1a3 reserved (read-only) 0x1a4 to 0x1df blank vco divider and clk input 0x1e0 vco divider blank vco divider 0x02 0x1e1 input clks reserved power- down clock input section reserved bypass vco divider 0x00 0x1e2 to 0x22a blank system 0x230 power-down and sync reserved power- down sync power- down distribution reference soft sync 0x00 0x231 blank 0x00 update all registers 0x232 update all registers blank update all registers (self-clearing) 0x00
ad9516-5 rev. a | page 52 of 76 register map descriptions table 48 through table 57 provide a detailed description of each of the control register functions. the registers are listed by hexadecimal address. a range of bits (for example, from bit 5 through bit 2) is indicated using a colon and brackets, as follows: [5:2]. table 48. serial port configuration reg. addr. (hex) bits name description 0x000 [7:4] mirrored, bits[3:0] bits[7:4] should always mirror bits[3:0], so that it does not matter whether the part is in msb or lsb first mode (see bit 1, register 0x 000). the user should set the bits as follows: bit 7 = bit 0. bit 6 = bit 1. bit 5 = bit 2. bit 4 = bit 3. 3 long instruction short/long instruction mode. this part uses lo ng instruction mode only, so this bit should always be set to 1b. 0: 8-bit instruction (short). 1: 16-bit instruction (long) (default). 2 soft reset soft reset. 1: soft reset; restores default values to internal registers. not self-clearing. must be cleared to 0b to complete reset operation. 1 lsb first msb or lsb data orientation. 0: data-oriented msb first; addressing decrements (default). 1: data-oriented lsb first; addressing increments. 0 sdo active selects unidirectional or bidirectional data transfer mode. 0: sdio pin used for write and read; sdo set to high impedance; bidirectional mode (default). 1: sdo used for read, sdio used for write; unidirectional mode. 0x003 [7:0] part id (read only) uniquely identi fies the dash version (-0 through -5) of the ad9516 . ad9516-0: 0x01. ad9516-1: 0x41. ad9516-2: 0x81. ad9516-3: 0x43. ad9516-4: 0xc3. ad9516-5: 0xc1. 0x004 0 read back active registers selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers.
ad9516-5 rev. a | page 53 of 76 table 49. pll reg. addr. (hex) bits name description 0x010 7 pfd polarity sets the pfd polarity. 0: positive; higher control voltag e produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. [6:4] cp current charge pump current (with cprset = 5.1 k). 6 5 4 icp (ma) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) [3:2] cp mode charge pump operating mode. 3 2 charge pump mode 0 0 high impedance state 0 1 force source current (pump up) 1 0 force sink current (pump down) 1 1 normal operation (default) [1:0] pll power-down pll operating mode. 1 0 mode 0 0 normal operation 0 1 asynchronous power-down (default) 1 0 normal operation 1 1 synchronous power-down 0x011 [7:0] 14-bit r divider, bits[7:0] (lsb) r divider lsbslower eight bits (default = 0x01). 0x012 [5:0] 14-bit r divider, bits[13:8] (msb) r divider msbsupper six bits (default = 0x00). 0x013 [5:0] 6-bit a counter a counter (p art of n divider) (default = 0x00). 0x014 [7:0] 13-bit b counter, bits[7:0] (lsb) b counter (part of n divider)lower eight bits (default = 0x03). 0x015 [4:0] 13-bit b counter, bits[12:8] (msb) b counter (part of n divider)upper five bits (default = 0x00). 0x016 7 set cp pin to v cp /2 sets the cp pin to one-half of the v cp supply voltage. 0: cp normal operation (default). 1: cp pin set to v cp /2. 6 reset r counter resets r counter (r di vider). this bit is not self-clearing. 0: normal (default). 1: holds the r counter in reset. 5 reset a and b counters resets a and b counters (part of n divider). 0: normal (default). this bit is not self-clearing. 1: holds the a and b counters in reset. 4 reset all counters resets r, a, and b counters. this bit is not self-clearing. 0: normal (default). 1: holds the r, a, and b counters in reset. 3 b counter bypass b counter bypass. this is vali d only when operating the prescaler in fd mode. 0: normal (default). 1: b counter is set to divide-by-1. this allows the prescaler setting to determine the divide for the n divider.
ad9516-5 rev. a | page 54 of 76 reg. addr. (hex) bits name description [2:0] prescaler p prescaler. dm = du al modulus, and fd = fixed divide. 2 1 0 mode prescaler 0 0 0 fd divide-by-1 0 0 1 fd divide-by-2 0 1 0 dm divide-by-2 (2/3 mode) 0 1 1 dm divide-by-4 (4/5 mode) 1 0 0 dm divide-by-8 (8/9 mode) 1 0 1 dm divide-by-16 (16/17 mode) 1 1 0 dm divide-by-32 (22/23 mode) (default) 1 1 1 fd divide-by-3 0x017 [7:2] selects the status pin signal. status pin control 7 6 5 4 3 2 level or dynamic signal signal at status pin 0 0 0 0 0 0 lvl ground (dc) (default) 0 0 0 0 0 1 dyn n divider output (after the delay) 0 0 0 0 1 0 dyn r divider output (after the delay) 0 0 0 0 1 1 dyn a divider output 0 0 0 1 0 0 dyn prescaler output 0 0 0 1 0 1 dyn pfd up pulse 0 0 0 1 1 0 dyn pfd down pulse 0 x x x x x lvl ground (dc); for all other cases of 0x0xxxx not specified the selections that follow are the same as for refmon : 1 0 0 0 0 0 lvl ground (dc) 1 0 0 0 0 1 dyn ref1 clock (different ial reference when in differential mode) 1 0 0 0 1 0 dyn ref2 clock (not available in differential mode) 1 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode) 1 0 0 1 0 1 lvl status of selected referenc e (status of differential reference); active high 1 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high 1 0 0 1 1 1 lvl status of ref1 frequency (active high) 1 0 1 0 0 0 lvl status of ref2 frequency (active high) 1 0 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of clk) 1 0 1 0 1 1 lvl status of clk frequency (active high) 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2) 1 0 1 1 0 1 lvl digital lock detect (dld); active high 1 0 1 1 1 0 lvl holdover active (active high) 1 0 1 1 1 1 lvl ld pin comparator output (active high) 1 1 0 0 0 0 lvl vs (pll supply) 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode) 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode) 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) 1 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode) 1 1 0 1 0 1 lvl status of selected referenc e (status of differential reference); active low 1 1 0 1 1 0 lvl status of unselected reference (not available in differential mode); active low 1 1 0 1 1 1 lvl status of ref1 frequency (active low) 1 1 1 0 0 0 lvl status of ref2 frequency (active low) 1 1 1 0 0 1 lvl (status of ref1 frequency) an d (s tatus of ref2 frequency) 1 1 1 0 1 0 lvl (dld) and (status of selected referenc e) and ( s tatus of clk) 1 1 1 0 1 1 lvl status of clk frequency (active low) 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1) 1 1 1 1 0 1 lvl digital lock detect (dld) (active low) 1 1 1 1 1 0 lvl holdover active (active low) 1 1 1 1 1 1 lvl ld pin comparator output (active low)
ad9516-5 rev. a | page 55 of 76 reg. addr. (hex) bits name description [1:0] 1 0 antibacklash pulse width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 antibacklash pulse width 1 1 2.9 0x018 [6:5] required consecutive number of pf d cycles with edges inside lock detect window before the dld indicates a locked condition. 6 5 pfd cycles to determine lock 0 0 5 (default) 0 1 16 1 0 64 lock detect counter 1 1 255 4 if the time difference of the rising edges at the inputs to the pfd is less than the lock detect window time, the digital lock detect flag is set. the flag remains set until the ti me difference is greater than the loss-of-lock threshold. 0: high range (default). digital lock detect window 1: low range. 3 digital lock detect operation. 0: normal lock detect operation (default). disable digital lock detect 1: disables lock detect. 0x019 [7:6] 7 6 action 0 0 does nothing on sync (default) 0 1 asynchronous reset 1 0 synchronous reset r, a, b counters sync pin reset 1 1 does nothing on sync [5:3] r path delay r path delay (default = 0x0); see table 2. [2:0] n path delay n path delay (default = 0x0); see table 2.
ad9516-5 rev. a | page 56 of 76 reg. addr. (hex) bits name description 0x01a 6 reference frequency monitor threshold sets the reference (ref1/ref2) frequency monitors detect ion threshold frequency. this does not affect the clk frequency monitors detection threshold (see table 12: re f1, ref2, and clk frequency status monitor parameter). 0: frequency valid if frequency is abov e the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold. [5:0] ld pin control se lects the ld pin signal. 5 4 3 2 1 0 level or dynamic signal signal at ld pin 0 0 0 0 0 0 lvl digital lock detect (high = lock, low = unlock) (default) 0 0 0 0 0 1 dyn p-channel, open-dra in lock detect (analog lock detect) 0 0 0 0 1 0 dyn n-channel, open-dra in lock detect (analog lock detect) 0 0 0 0 1 1 hiz high-z ld pin 0 0 0 1 0 0 cur current source lock detect (110 a when dld is true) 0 x x x x x lvl ground (dc); for all other cases of 0x0xxxx not specified the selections that follow are the same as for refmon: 1 0 0 0 0 0 lvl ground (dc) 1 0 0 0 0 1 dyn ref1 clock (different ial reference when in differential mode) 1 0 0 0 1 0 dyn ref2 clock (not available in differential mode) 1 0 0 0 1 1 dyn selected reference to pll (d ifferential reference when in differential mode) 1 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode) 1 0 0 1 0 1 lvl status of selected referenc e (status of differential reference); active high 1 0 0 1 1 0 lvl status of unselected reference (not available in differential mode); active high 1 0 0 1 1 1 lvl status of ref1 frequency (active high) 1 0 1 0 0 0 lvl status of ref2 frequency (active high) 1 0 1 0 0 1 lvl (status of ref1 freq uency) and (status of ref2 frequency) 1 0 1 0 1 0 lvl (dld) and (status of selected reference) and (status of clk) 1 0 1 0 1 1 lvl status of clk frequency (active high) 1 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2) 1 0 1 1 0 1 lvl digital lock detect (dld); active high 1 0 1 1 1 0 lvl holdover active (active high) 1 0 1 1 1 1 lvl not available; do not use 1 1 0 0 0 0 lvl vs (pll supply) 1 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode) 1 1 0 0 1 0 dyn ref2 clock (not available in differential mode) 1 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) 1 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode) 1 1 0 1 0 1 lvl status of selected referenc e (status of differential reference); active low 1 1 0 1 1 0 lvl status of unselected referenc e (not available in differential mode); active low 1 1 0 1 1 1 lvl status of ref1 frequency (active low) 1 1 1 0 0 0 lvl status of ref2 frequency (active low) 1 1 1 0 0 1 lvl (status of ref1 frequency) and (status of ref2 frequency) 1 1 1 0 1 0 lvl (dld) and (status of selected reference) and (status of clk) 1 1 1 0 1 1 lvl status of clk frequency (active low) 1 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1) 1 1 1 1 0 1 lvl digital lock detect (dld); active low 1 1 1 1 1 0 lvl holdover active (active low) 1 1 1 1 1 1 lvl not available; do not use 0x01b 7 clk frequency monitor enables or disables clk frequency monitor. 0: disables clk frequency monitor (default). 1: enables clk frequency monitor. 6 ref2 ( refin ) frequency monitor enables or disables ref2 frequency monitor. 0: disables ref2 frequency monitor (default). 1: enables ref2 frequency monitor. 5 ref1 (refin) frequency monitor ref1 (refin) frequency monitor enable; this is for both ref1 (single-ended) and re fin (differential) inputs (as selected by differential reference mode). 0: disables ref1 (refin) frequency monitor (default). 1: enables ref1 (refin) frequency monitor.
ad9516-5 rev. a | page 57 of 76 reg. addr. (hex) bits name description [4:0] selects the signal that is connected to the refmon pin. refmon pin control 4 3 2 1 0 level or dynamic signal signal at refmon pin 0 0 0 0 0 lvl ground (dc) (default) 0 0 0 0 1 dyn ref1 clock (different ial reference when in differential mode) 0 0 0 1 0 dyn ref2 clock (not available in differential mode) 0 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) 0 0 1 0 0 dyn unselected reference to pll (not available in differential mode) 0 0 1 0 1 lvl status of selected reference (status of differential reference); active high 0 0 1 1 0 lvl status of unse lected reference (not available in differential mode); active high 0 0 1 1 1 lvl status of ref1 frequency (active high) 0 1 0 0 0 lvl status of ref2 frequency (active high) 0 1 0 0 1 lvl (status of ref1 freq uency) and (status of ref2 frequency) 0 1 0 1 0 lvl (dld) and (status of se lected reference) and (status of clk) 0 1 0 1 1 lvl status of clk frequency (active high) 0 1 1 0 0 lvl selected reference (low = ref1, high = ref2) 0 1 1 0 1 lvl digital lock detect (dld); active low 0 1 1 1 0 lvl holdover active (active high) 0 1 1 1 1 lvl ld pin comparator output (active high) 1 0 0 0 0 lvl vs (pll supply) 1 0 0 0 1 dyn ref1 clock (differential reference when in differential mode) 1 0 0 1 0 dyn ref2 clock (not available in differential mode) 1 0 0 1 1 dyn selected reference to pll (differential reference when in differential mode) 1 0 1 0 0 dyn unselected reference to pll (not available when in differential mode) 1 0 1 0 1 lvl status of selected referenc e (status of differential reference); active low 1 0 1 1 0 lvl status of unse lected reference (not available in differential mode); active low 1 0 1 1 1 lvl status of ref1 frequency (active low) 1 1 0 0 0 lvl status of ref2 frequency (active low) 1 1 0 0 1 lvl (status of ref1 frequency) an d (s tatus of ref2 frequency) 1 1 0 1 0 lvl (dld) and (status of selected referenc e) and ( s tatus of clk) 1 1 0 1 1 lvl status of clk frequency (active low) 1 1 1 0 0 lvl selected reference (low = ref2, high = ref1) 1 1 1 0 1 lvl digital lock detect (dld); active low 1 1 1 1 0 lvl holdover active (active low) 1 1 1 1 1 lvl ld pin comparator output (active low) 0x01c 7 disables or enables the switchover deglitch circuit. 0: enables switchover deglitch circuit (default). disable switchover deglitch 1: disables switchover deglitch circuit. 6 select ref2 if register 0x01c[ 5] = 0, selects reference for pll. 0: select ref1 (default). 1: select ref2. 5 use ref_sel pin if register 0x01c[4] = 0 (m anual), sets method of pll reference selection. 0: uses register 0x01c[6] (default). 1: uses ref_sel pin. 4 reserved 0: default. 3 reserved 0: default. 2 this bit turns the ref2 power on. 0: ref2 power off (default). ref2 power-on 1: ref2 power on. 1 this bit turns the ref1 power on. 0: ref1 power off (default). ref1 power-on 1: ref1 power on. 0 selects the pll reference mode, diffe rential or single-ended. single-ended must be selected for the automatic reference switchover or ref1 and ref2 to work. 0: single-ended reference mode (default). differential reference 1: differential reference mode.
ad9516-5 rev. a | page 58 of 76 reg. addr. (hex) bits name description 0x01d 4 disables the pll status register readback. 0: pll status register enable (default). pll status register disable 1: pll status register disable. 3 enables the ld pin voltage comparator. this function is used with the ld pin current source lock detect mode. when in the internal (automatic) holdover mode, th is function enables the use of the voltage on the ld pin to determine if the pll was previously in a locked state (see figure 41 ). otherwise, this function can be used with the refmon and status pins to monitor the voltage on the ld pin. 0: disables ld pin comparator; internal/automatic hol dover controller treats this pin as true/high (default). ld pin comparator enable 1: enables ld pin comparator. 2 along with register 0x01d[0], enables the holdover function. 0: holdover disabled (default). holdover enable 1: holdover enabled. 1 enables the external hold control through the sync pin. (this disables the internal holdover mode.) 0: automatic holdover modeholdover controll ed by automatic holdover circuit (default). external holdover control 1: external holdover m odeholdover controlled by sync pin. 0 along with register 0x01d[2], enables the holdover function. 0: holdover disabled (default). holdover enable 1: holdover enabled. read-only register. indicates if the part is in the holdover state (see figure 41 ). this is not the same as holdover enabled. 0: not in holdover. 0x01f 5 holdover active 1: holdover state active. 4 read-only register. indicates which pll reference is selected as the input to the pll. 0: ref1 selected (or differential reference if in differential mode). ref2 selected 1: ref2 selected. 3 read-only register. indicates if the clk frequency is greater than the threshold (see table 12 : ref1, ref2, and clk frequency status monitor). 0: clk frequency is less than the threshold. clk frequency > threshold 1: clk frequency is grea ter than the threshold. read-only register. indicates if the frequency of the signal at ref2 is greater than the threshold frequency set by register 0x01a[6]. 0: ref2 frequency is less than threshold frequency. 2 ref2 frequency > threshold 1: ref2 frequency is greate r than threshold frequency. 1 read-only register. indicates if the frequency of the sign al at ref2 is greater than the threshold frequency set by register 0x01a[6]. 0: ref1 frequency is less than threshold frequency. ref1 frequency > threshold 1: ref1 frequency is greate r than threshold frequency. 0 read-only register. digital lock detect. 0: pll is not locked. digital lock detect 1: pll is locked.
ad9516-5 rev. a | page 59 of 76 table 50. fine delay adjustout6 to out9 b reg. addr. (hex) its name description 0x0a0 0 bypasses or uses the delay function. 0: uses the delay function. out6 delay bypass 1: bypasses the delay function (default). 0x0a1 [5:3] out6 ramp capacitors selects the number of ramp capacitors used by the delay function. the combination of the number of capacitors and the ramp curren t sets the full-scale delay. 5 4 3 number of capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] out6 ramp current ramp current for the delay function. the combination of the number of capacitors and the ramp current sets the full-scale delay. 2 1 0 current (a) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0a2 [5:0] out6 delay fraction selects the fraction of the full-scale delay desired (6-bit binary). a setting of 000000b gives zero delay. only delay values of up to 47 decimals (101111b; 0x02f) are supported (default: 0x00). 0x0a3 0 bypasses or uses the delay function. 0: uses the delay function. out7 delay bypass 1: bypasses the delay function (default). 0x0a4 [5:3] out7 ramp capacitors selects the number of ramp capacitors used by the delay function. the combination of the number of the capacitors and the ramp curren t sets the full-scale delay. 5 4 3 number of capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1
ad9516-5 rev. a | page 60 of 76 reg. addr. (hex) bits name description 0x0a4 [2:0] out7 ramp current ramp current for the delay function. the combinatio n of the number of capacitors and the ramp current sets the full-scale delay. 2 1 0 current (a) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0a5 [5:0] out7 delay fraction selects the fraction of the full-scale delay desired (6-bit binary). a setting of 000000b gives zero delay. only delay values of up to 47 decimals (101111b; 0x02f) are supported (default: 0x00). 0x0a6 0 bypasses or uses the delay function. 0: uses the delay function. out8 delay bypass 1: bypasses the delay function (default). 0x0a7 [5:3] out8 ramp capacitors selects the number of ramp capacitors used by the delay function. the combination of the number of capacitors and the ramp curren t sets the full-scale delay. 5 4 3 number of capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] out8 ramp current ramp current for the delay function. the combinatio n of the number of capacitors and the ramp current sets the full-scale delay. 2 1 0 current (a) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0a8 [5:0] out8 delay fraction selects the fraction of the full-scale delay desired (6-bit binary). a setting of 000000b gives zero delay. only delay values of up to 47 decimals (101111b; 0x02f) are supported (default: 0x00). 0x0a9 [0] bypasses or uses the delay function. 0: uses the delay function. out9 delay bypass 1: bypasses the delay function (default).
ad9516-5 rev. a | page 61 of 76 reg. addr. (hex) bits name description 0x0aa [5:3] out9 ramp capacitors selects the number of ramp capacitors used by the delay function. the combination of the number of capacitors and the ramp curren t sets the full-scale delay. 5 4 3 number of capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] out9 ramp current ramp current for the delay function. the combinatio n of the number of capacitors and the ramp current sets the full-scale delay. 2 1 0 current value (a) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0ab [5:0] out9 delay fraction selects the fraction of the full-scale delay desired (6-bit binary). a setting of 000000b gives zero delay. only delay values of up to 47 decimals (101111b; 0x02f) are supported (default: 0x00). table 51. lvpecl outputs reg. addr. (hex) bits name description 0x0f0 4 out0 invert sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] sets the lvpecl output differential voltage (v od ). 3 2 v od (mv) 0 0 400 0 1 600 1 0 780 (default) out0 lvpecl differential voltage 1 1 960 [1:0] lvpecl power-down modes. 1 0 mode output 0 0 normal operation (default) on 0 1 partial power-down, reference on; use only if there are no external load resistors off 1 0 partial power-down, reference on; safe lvpecl power-down off out0 power-down 1 1 total power-down, reference off; use only if there are no external load resistors off
ad9516-5 rev. a | page 62 of 76 reg. addr. (hex) bits name description 0x0f1 4 sets the output polarity. 0: noninverting (default). out1 invert 1: inverting. [3:2] sets the lvpecl output differential voltage (v od ). 3 2 v od (mv) 0 0 400 0 1 600 1 0 780 (default) out1 lvpecl differential voltage 1 1 960 [1:0] lvpecl power-down modes. 1 0 mode output 0 0 normal operation on 0 1 partial power-down, reference on; use only if there are no external load resistors off 1 0 partial power-down, reference on; safe lvpecl power-down (default) off out1 power-down 1 1 total power-down, reference off; use only if there are no external load resistors off 0x0f2 4 sets the output polarity. 0: noninverting (default). out2 invert 1: inverting. [3:2] sets the lvpecl output differential voltage (v od ). 3 2 v od (mv) 0 0 400 0 1 600 1 0 780 (default) out2 lvpecl differential voltage 1 1 960 [1:0] lvpecl power-down modes. 1 0 mode output 0 0 normal operation (default) on 0 1 partial power-down, reference on; use only if there are no external load resistors off 1 0 partial power-down, reference on, safe lvpecl power-down off out2 power-down 1 1 total power-down, reference off; use only if there are no external load resistors off 0x0f3 4 sets the output polarity. 0: noninverting (default). out3 invert 1: inverting. [3:2] sets the lvpecl output differential voltage (v od ). 3 2 v od (mv) 0 0 400 0 1 600 1 0 780 (default) out3 lvpecl differential voltage 1 1 960 [1:0] lvpecl power-down modes. out3 power-down 1 0 mode output 0 0 normal operation on 0 1 partial power-down, reference on; use only if there are no external load resistors off 1 0 partial power-down, reference on, safe lvpecl power-down (default) off 1 1 total power-down, reference off; use only if there are no external load resistors off
ad9516-5 rev. a | page 63 of 76 reg. addr. (hex) bits name description 0x0f4 4 sets the output polarity. 0: noninverting (default). out4 invert 1: inverting. [3:2] sets the lvpecl output differential voltage (v od ). 3 2 v od (mv) 0 0 400 0 1 600 1 0 780 (default) out4 lvpecl differential voltage 1 1 960 [1:0] lvpecl power-down modes. 1 0 mode output 0 0 normal operation on 0 1 partial power-down, reference on; use only if there are no external load resistors off 1 0 partial power-down, reference on, safe lvpecl power-down off out4 power-down 1 1 total power-down, reference off; use only if there are no external load resistors off 0x0f5 4 sets the output polarity. 0: noninverting (default). out5 invert 1: inverting. [3:2] sets the lvpecl output differential voltage (v od ). 3 2 v od (mv) 0 0 400 0 1 600 1 0 780 (default) out5 lvpecl differential voltage 1 1 960 [1:0] lvpecl power-down modes. 1 0 mode output 0 0 normal operation on 0 1 partial power-down, reference on; use only if there are no external load resistors off 1 0 partial power-down, reference on, safe lvpecl power-down (default) off out5 power-down 1 1 total power-down, reference off; use only if there are no external load resistors off
ad9516-5 rev. a | page 64 of 76 table 52. lvds/cmos outputs reg. addr. (hex) bits name description 0x140 [7:5] out6 output polarity in cmos mode, bits[7:5] select the output polarity of each cmos output. in lvds mode, only bit 5 determines lvds polarity. 7 6 5 out6a (cmos) out6b (cmos) out6 (lvds) 0 0 0 noninverting inverting noninverting 0 1 0 noninverting noninverting noninverting (default) 1 0 0 inverting inverting noninverting 1 1 0 inverting noninverting noninverting 0 0 1 inverting noninverting inverting 0 1 1 inverting inverting inverting 1 0 1 noninverting noninverting inverting 1 1 1 noninverting inverting inverting 4 out6 cmos b in cmos mode, turns on/off the cm os b output. this has no effect in lvds mode. 0: turns off the cmos b output (default). 1: turns on the cmos b output. 3 out6 select lvds/cmos selects lvds or cmos logic levels. 0: lvds (default). 1: cmos. [2:1] out6 lvds output current sets output current le vel in lvds mode. this has no effect in cmos mode. 2 1 current (ma) recommended termination () 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 out6 power-down power-down output (lvds/cmos). 0: powers on (default). 1: powers off. 0x141 [7:5] out7 output polarity in cmos mode, bits[7:5] select the output polarity of each cmos output. in lvds mode, only bit 5 determines lvds polarity. 7 6 5 out7a (cmos) out7b (cmos) out7 (lvds) 0 0 0 noninverting inverting noninverting 0 1 0 noninverting noninverting noninverting (default) 1 0 0 inverting inverting noninverting 1 1 0 inverting noninverting noninverting 0 0 1 inverting noninverting inverting 0 1 1 inverting inverting inverting 1 0 1 noninverting noninverting inverting 1 1 1 noninverting inverting inverting 4 out7 cmos b in cmos mode, turns on/off the cm os b output. this has no effect in lvds mode. 0: turns off the cmos b output (default). 1: turns on the cmos b output. 3 out7 select lvds/cmos selects lvds or cmos logic levels. 0: lvds (default). 1: cmos. [2:1] out7 lvds output current sets output current le vel in lvds mode. this has no effect in cmos mode. 2 1 current (ma) recommended termination () 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50
ad9516-5 rev. a | page 65 of 76 reg. addr. (hex) bits name description 0 out7 power-down power-down output (lvds/cmos). 0: powers on. 1: powers off (default). 0x142 [7:5] out8 output polarity in cmos mode, bits[7:5] select the output polarity of each cmos output. in lvds mode, only bit 5 determines lvds polarity. 7 6 5 out8a (cmos) out8b (cmos) out8 (lvds) 0 0 0 noninverting inverting noninverting 0 1 0 noninverting noninverting noninverting (default) 1 0 0 inverting inverting noninverting 1 1 0 inverting noninverting noninverting 0 0 1 inverting noninverting inverting 0 1 1 inverting inverting inverting 1 0 1 noninverting noninverting inverting 1 1 1 noninverting inverting inverting 4 out8 cmos b in cmos mode, turns on/off the cm os b output. there is no effect in lvds mode. 0: turns off the cmos b output (default). 1: turns on the cmos b output. 3 out8 select lvds/cmos selects lvds or cmos logic levels. 0: lvds (default). 1: cmos. [2:1] out8 lvds output current sets output current le vel in lvds mode. this has no effect in cmos mode. 2 1 current (ma) recommended termination () 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 out8 power-down power-down output (lvds/cmos). 0: powers on (default). 1: powers off. 0x143 [7:5] out9 output polarity in cmos mode, bits[7:5] select the output polarity of each cmos output. in lvds mode, only bit 5 determines lvds polarity. 7 6 5 out9a (cmos) out9b (cmos) out9 (lvds) 0 0 0 noninverting inverting noninverting 0 1 0 noninverting noninverting noninverting (default) 1 0 0 inverting inverting noninverting 1 1 0 inverting noninverting noninverting 0 0 1 inverting noninverting inverting 0 1 1 inverting inverting inverting 1 0 1 noninverting noninverting inverting 1 1 1 noninverting inverting inverting 4 out9 cmos b in cmos mode, turns on/off the cm os b output. this has no effect in lvds mode. 0: turns off the cmos b output (default). 1: turns on the cmos b output. 3 out9 select lvds/cmos selects lvds or cmos logic levels. 0: lvds (default). 1: cmos.
ad9516-5 rev. a | page 66 of 76 reg. addr. (hex) bits name description [2:1] out9 lvds output current sets output current le vel in lvds mode. this has no effect in cmos mode. 2 1 current (ma) recommended termination () 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 [0] out9 power-down power-down output (lvds/cmos). 0: powers on. 1: powers off (default). table 53. lvpecl channel dividers reg. addr. (hex) bits name description 0x190 [7:4] divider 0 low cycles number of clock cycles (minus 1) of the divi der 0 input during which the divider 0 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). [3:0] divider 0 high cycles number of clock cycles (minus 1) of the divi der 0 input during which the divider 0 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). 0x191 7 divider 0 bypass bypasses and powers down the divider; routes input to the divider output. 0: uses the divider. 1: bypasses the divider (default). 6 divider 0 nosync no sync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal. 5 divider 0 force high forces divider output to high. this operation requir es that the divider 0 nosync bit (bit 6) also be set. this bit has no effect if the divider 0 bypass bit (bit 7) is set. 0: normal operation (default). 1: divider output forced to the setting of the divider 0 start high bit. 4 divider 0 start high selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] divider 0 phase offset phase offset (default: 0x0). 0x192 1 divider 0 direct to output connects out0 an d out1 to divider 0 or directly to clk input. 0: out0 and out1 are connected to divider 0 (default). 1: if register 0x1e1[0] = 0b, the clk is routed directly to out0 and out1. if register 0x1e1[0] = 1b, there is no effect. 0 divider 0 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x193 [7:4] divider 1 low cycles number of clock cycles (minus 1) of the divide r 1 input during which the divider 1 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0xb). [3:0] divider 1 high cycles number of clock cycles (minus 1) of the divide r 1 input during which the divider 1 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0xb). 0x194 7 divider 1 bypass bypasses and powers down the divider; routes in put to divider output. 0: uses divider (default). 1: bypasses divider. 6 divider 1 nosync no sync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal.
ad9516-5 rev. a | page 67 of 76 reg. addr. (hex) bits name description 5 divider 1 force high forces divider output to high. this operation requir es that the divider 1 nosync bit (bit 6) also be set. this bit has no effect if the divider 1 bypass bit (bit 7) is set. 0: normal operation (default). 1: divider output forced to the setting of the divider 1 start high bit. 4 divider 1 start high selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] divider 1 phase offset phase offset (default: 0x0). 0x195 1 divider 1 direct to output connects out2 and out3 to divider 1 or directly to clk input. 0: out2 and out3 are connected to divider 1 (default). 1: if register 0x1e1[0] = 0b, the clk is routed directly to out2 and out3. if register 0x1e1[0] = 1b, this has no effect. 0 divider 1 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x196 [7:4] divider 2 low cycles number of clock cycles (minus 1) of the divide r 2 input during which the divider 2 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). [3:0] divider 2 high cycles number of clock cycles (minus 1) of the divide r 2 input during which the divider 2 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0). 0x197 7 divider 2 bypass bypasses and powers down the divider; route in put to divider output. 0: uses divider (default). 1: bypasses divider. 6 divider 2 nosync no sync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal. 5 divider 2 force high forces divider output to high. this operation requir es that the divider 2 nosync bit (bit 6) also be set. this bit has no effect if the divider 2 bypass bit (bit 7) is set. 0: normal operation (default). 1: divider output forced to the setting of the divider 2 start high bit. 4 divider 2 start high selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] divider 2 phase offset phase offset (default: 0x0). 0x198 1 divider 2 direct to output connects out4 and out5 to divider 2 or directly to clk input. 0: out4 and out5 are connected to divider 2 (default). 1: if 0x1e1[0] = 0b, the clk is routed directly to out4 and out5. if 0x1e1[0] = 1b, there is no effect. 0 divider 2 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction.
ad9516-5 rev. a | page 68 of 76 table 54. lvds/cmos channel dividers reg. addr. (hex) bits name description 0x199 [7:4] low cycles divider 3.1 number of clock cycles (minus 1) of the divide r 3.1 input during which the divider 3.1 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2). [3:0] high cycles divider 3.1 number of clock cycles (minus 1) of the divide r 3.1 input during which the divider 3.1 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2). 0x19a [7:4] phase offset divider 3.2 refers to lvds/cmo s channel divider function description (default: 0x0). [3:0] phase offset divider 3.1 refers to lvds/cmos channel divider function description (default: 0x0). 0x19b [7:4] low cycles divider 3.2 number of clock cycles (minus 1) of the divide r 3.2 input during which the divider 3.2 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1). [3:0] high cycles divider 3.2 number of clock cycles (minus 1) of the divide r 3.2 input during which the divider 3.2 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1). 0x19c 5 bypass divider 3.2 bypasses (and powers down ) 3.2 divider logic, routes clock to 3.2 output. 0: does not bypass (default). 1: bypasses. 4 bypass divider 3.1 bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output. 0: does not bypass (default). 1: bypasses. 3 divider 3 nosync no sync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal. 2 divider 3 force high forces divider 3 output high. requir es that the divider 3 nosync bit (bit 3) also be set. 0: forces low (default). 1: forces high. 1 start high divider 3.2 divider 3.2 starts high/low. 0: starts low (default). 1: starts high. 0 start high divider 3.1 divider 3.1 starts high/low. 0: starts low (default). 1: starts high. 0x19d 0 divider 3 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x19e [7:4] low cycles divider 4.1 number of clock cycles (minus 1) of the divide r 4.1 input during which the divider 4.1 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2). [3:0] high cycles divider 4.1 number of clock cycles (minus 1) of the divide r 4.1 input during which the divider 4.1 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2). 0x19f [7:4] phase offset divider 4.2 refers to lvdscm os channel divider function description (default: 0x0). [3:0] phase offset divider 4.1 refers to lvdscmos channel divider function description (default: 0x0). 0x1a0 [7:4] low cycles divider 4.2 number of clock cycles (minus 1) of the divide r 4.2 input during which the divider 4.2 output stays low. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1). [3:0] high cycles divider 4.2 number of clock cycles (minus 1) of the divide r 4.2 input during which the divider 4.2 output stays high. a value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1). 0x1a1 5 bypass divider 4.2 bypasses (and powers down) 4.2 divider logic, routes clock to 4.2 output. 0: does not bypass (default). 1: bypasses. 4 bypass divider 4.1 bypasses (and powers down) 4.1 divider logic, routes clock to 4.1 output. 0: does not bypass (default). 1: bypasses. 3 divider 4 nosync no sync. 0: obeys chip-level sync signal (default). 1: ignores chip-level sync signal.
ad9516-5 rev. a | page 69 of 76 reg. addr. (hex) bits name description 2 divider 4 force high forces divider 4 output high. requires that the divider 4 nosync bit (bit 3) also be set. 0: forces low (default). 1: forces high. 1 start high divider 4.2 divider 4.2 starts high/low. 0: starts low (default). 1: starts high. 0 start high divider 4.1 divider 4.1 starts high/low. 0: starts low (default). 1: starts high. 0x1a2 0 divider 4 dccoff duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. table 55. vco divider and clk input reg. addr. (hex) bits name description 0x1e0 [2:0] vco divider 2 1 0 divide 0 0 0 2 0 0 1 3 0 1 0 4 (default) 0 1 1 5 1 0 0 6 1 0 1 output static 1 1 0 output static 1 1 1 output static 0x1e1 4 power-down clock input section powers down the clock input section (including clk buffer, vco divider, and clk tree). 0: normal operation (default). 1: powers down. 0 bypass vco divider bypasses or uses the vco divider. 0: uses vco divider (default). 1: bypasses vco divider. table 56. system reg. addr. (hex) bits name description 230 2 power-down sync powers down the sync function. 0: normal operation of the sync function (default). 1: powers down the sync circuitry. 1 power-down distribution reference powers down the reference for distribution section. 0: normal operation of the referenc e for the distribution section (default). 1: powers down the reference for the distribution section. 0 soft sync the soft sync bit works the same as the sync pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1- to-0 transition triggers a sync. 0: same as sync high (default). 1: same as sync low.
ad9516-5 rev. a | page 70 of 76 table 57. update all registers reg. addr. (hex) bits name description 0x232 0 update all registers this bit must be set to 1 to transfer the contents of the buffer registers into the active registers, which happens on the next sclk rising edge. this bi t is self-clearing; that is, it does not have to be set back to 0. 1: updates all active registers to the contents of the buffer registers (self-clearing).
ad9516-5 rev. a | page 71 of 76 applications information considering an ideal adc of infinite resolution, where the step size and quantization error can be ignored, the available snr can be expressed approximately by frequency planning using the ad9516 the ad9516 is a highly flexible pll. when choosing the pll settings and version of the ad9516 , keep in mind the following guidelines. ? ? ? ? ? ? ? ? = ja tf snr 2 1 log20(db) the ad9516 has the following four frequency dividers: the reference (or r) divider, the feedback (or n) divider, the vco divider, and the channel divider. when trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the vco divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. where: f a is the highest analog frequency being digitized. t j is the rms jitter on the sampling clock. figure 58 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (enob). f a (mhz) snr (db) enob 10 1k 100 30 40 50 60 70 80 90 100 110 6 8 10 12 14 16 18 t j = 1 0 0 f s 2 0 0 f s 4 0 0 f s 1 p s 2 p s 1 0 p s snr = 20log 1 2 within the ad9516 family, lower vco frequencies generally result in slightly lower jitter. the difference in integrated jitter (from 12 khz to 20 mhz offset) for the same output frequency is usually less than 150 fs over the entire vco frequency range (1.45 ghz to 2.95 ghz) of the ad9516 family. if the desired frequency plan can be achieved with a version of the ad9516 that has a lower vco frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter. however, choosing a higher vco frequency may result in more flexibility in frequency planning. choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the pll loop bandwidth in either direction. figure 58. snr and enob vs. analog input frequency see the an-756 application note , sampled systems and the effects of clock phase noise and jitter ; and the an-501 application note , aperture uncertainty and adc system performance , at www.analog.com . adisimclk is a powerful pll modeling tool that can be downloaded from www.analog.com . it is a very accurate tool for determining the optimal loop filter for a given application. using the ad9516 outputs for adc clock applications many high performance adcs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy pcb. (distributing a single-ended clock on a noisy pcb may result in coupled noise on the sample clock. differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) the ad9516 features both lvpecl and lvds outputs that provide differential clock outputs, which enable clock solutions that maximize converter snr performance. the input requirements of the adc (differential or single-ended, logic level, and termination) should be considered when selecting the best clocking/converter solution. any high speed adc is extremely sensitive to the quality of its sampling clock. an adc can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. the theoretical snr of an adc is limited by the adc resolution and the jitter on the sampling clock.
ad9516-5 rev. a | page 72 of 76 lvpecl clock distribution the lvpecl outputs of the ad9516 provide the lowest jitter clock signals that are available from the ad9516 . the lvpecl outputs (because they are open emitter) require a dc termination to bias the output transistors. the simplified equivalent circuit in figure 47 shows the lvpecl output stage. in most applications, an lvpecl far-end thevenin termination (see figure 59 ) or y-termination (see figure 60 ) is recommended. in each case, the v s of the receiving buffer should match the v s_lvpecl . if it does not match, ac coupling is recommended (see figure 61 ). the resistor network is designed to match the transmission line impedance (50 ) and the switching threshold (v s ? 1.3 v). v s_lvpecl lvpecl 50 ? 50 ? single-ended (not coupled) v s v s_drv lvpecl 127 ? 127 ? 83 ? 07972-045 figure 59. dc-coupled 3.3 v lvpe cl far-end thevenin termination v s_lvpecl lvpecl z 0 = 50 ? v s = 3.3v lvpecl 50 ? 50 ? 50 ? z 0 = 50 ? 0 7972-147 figure 60. dc-coupled 3.3 v lvpecl y-termination v s_lvpecl lvpecl 100 ? differential (coupled) transmission line v s lvpecl 100 ? 0.1nf 0.1nf 200 ? 200 ? 0 7972-046 figure 61. ac-coupled lvpecl with parallel transmission line lvpecl y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower lvpecl driver. this can be an important consideration when driving long trace lengths but is usually not an issue. in the case shown in figure 60 , where v s_lvpecl = 2.5 v, the 50 termination resistor connected to ground should be changed to 19 . thevenin-equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below v ol of the lvpecl driver. in this case, v s_lvpecl on the ad9516 should equal v s of the receiving buffer. although the resistor combination shown in figure 60 results in a dc bias point of v s_lvpecl ? 2 v, the actual common-mode voltage is v s_lvpecl ? 1.3 v because additional current flows from the ad9516 lvpecl driver through the pull- down resistor. the circuit is identical when v s_lvpecl = 2.5 v, except that the pull-down resistor is 62.5 and the pull-up resistor is 250 . lvds clock distribution the ad9516 provides four clock outputs (out6 to out9) that are selectable as either cmos or lvds level outputs. lvds is a differential output option that uses a current mode output stage. the nominal current is 3.5 ma, which yields a 350 mv output swing across a 100 resistor. an output current of 7 ma is also available in cases where a larger output swing is required. the lvds output meets or exceeds all ansi/tia/eia-644 specifications. a recommended termination circuit for the lvds outputs is shown in figure 62 . v s lvds 100? differential (coupled) v s lvds 100? 07972-047 figure 62. lvds output termination see the an-586 application note , lvds data outputs for high- speed analog-to-digital converters for more information on lvds.
ad9516-5 rev. a | page 73 of 76 cmos cmos 10? 60.4 ? (1.0 inch) microstrip 07972-076 cmos clock distribution the ad9516 provides four clock outputs (out6 to out9) that are selectable as either cmos or lvds level outputs. when selected as cmos, each output becomes a pair of cmos outputs, each of which can be individually turned on or off and set as noninverting or inverting. these outputs are 3.3 v cmos compatible. figure 63. series termination of cmos output termination at the far end of the pcb trace is a second option. the cmos outputs of the ad9516 do not supply enough current to provide a full voltage swing with a low impedance resistive, far- end termination, as shown in figure 64 . the far-end termination network should match the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet receiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. whenever single-ended cmos clocking is used, some general guidelines should be followed. point-to-point nets should be designed such that a driver has only one receiver on the net, if possible. this allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. the value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). cmos outputs are also limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity. cmos cmos 10? 50? 100? 100? v s 0 7972-077 figure 64. cmos output wi th far-end termination because of the limitations of single-ended cmos clocking, consider using differential outputs when driving high speed signals over long traces. the ad9516 offers both lvpecl and lvds outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
ad9516-5 rev. a | page 74 of 76 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 65. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9516-5bcpz ?40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-4 ad9516-5bcpz-reel7 ?40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-4 ad9516-5/pcbz evaluation board 1 z = rohs compliant part.
ad9516-5 rev. a | page 75 of 76 notes
ad9516-5 rev. a | page 76 of 76 notes ?2009C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07972-0-8/11(a)

▲Up To Search▲

Price & Availability of AD9516-5PCBZ

	To Download AD9516-5PCBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .